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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
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*SIS...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:...
***Configurations:...
***Features:
o Support Intel/AMD/Cyrix Pentium CPU and Other Compatible CPU
Host Bus at 60/66 MHz and 3.3V Bus Interface
− Support the Pipelined Address of Pentium compatible CPU
− Support the Linear Address Mode of Cyrix CPU
o Support the Pipelined Address Mode of Pentium CPU
o Fully Compliant to A.G.P. Revision 1.0 Specification
o Meet PC97 Requirements
o Supports PCI Revision 2.1 Specification
o Integrated Second Level (L2) Cache Controller
- Write Back Cache Mode
- Support L2 Cache Flushing for entire L2 cache or specific
4K page
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 32K bits Dirty SRAM
- Integrated 32K bits Invalid SRAM
- Support Pipelined Burst SRAM
- Support 256K/512K/1MBytes Cache Sizes
- Cache Hit Read/Write Cycle of 3-1-1-1
- Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
- Support Single Read Allocation for L2 Cache
- Support Concurrency of CPU to L2 cache and A.G.P. master to
DRAM accesses
o Integrated DRAM Controller
- Support 6 RAS Lines for FPM/EDO/SDRAM DIMMs/SIMMs
- Support 2Mbytes to 768Mbytes of main memory
- Support Cacheable DRAM Sizes up to 256 MBytes.
- Support 256K/512K/1M/2M/4M/8M/16Mx N FPM/EDO/SDRAM DRAM
- Support 64 Mb DRAM Technology
- Support Parity Checker or ECC Function
- Support 3.3V or 5V DRAM
- Supports Symmetrical and Asymmetrical DRAM
- Support Concurrent Write Back
- Support CAS before RAS Refresh, Self Refresh
- Support Relocation of System Management Memory
- Programmable CAS#, RAS#, RAMWE# and MA Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Support FPM DRAM 5/6-3-3-3(-3-3-3-3) Burst Read Cycles
- Support EDO DRAM 5/6-2-2-2(-2-2-2-2) Burst Read Cycles
- Support SDRAM 5/6/7-1-1-1(-2/3-1-1-1) Burst Read Cycles
- Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Two Programmable Non-cacheable Regions
- Option to Disable Local Memory in Non-cacheable Regions
- Shadow RAM in Increments of 16 Kbytes
- Pseudo Directory/Page Scheme for Mapping Graphical Texture
Access to Physical Memory Address
- Built-in 8 Way Associative/16 Entries GART cache to Minimize the
Number of Memory Bus Cycles Required for Accessing Graphical
Texture Memory
- Programmable Counters to Ensure Guaranteed Minimum Access Time
for A.G.P., CPU, and PCI accesses
o Provides High Performance PCI Arbiter.
- Support up to 5 PCI Masters
- Support Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Support Concurrency between CPU to Memory and PCI to PCI
- Support Concurrency between CPU to 33Mhz PCI Access and 33Mhz
PCI to A.G.P. Access
- Support Concurrency between CPU to 66Mhz PCI Access and A.G.P.
to 33Mhz PCI Access
- Programmable Timers Ensure Guaranteed Minimum Access Time for
PCI Bus Masters, and CPU
o Integrated Host-to-PCI Bridge
- Support Asynchronous and Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Zero Wait State Burst Cycles
- Support IDE Posted Write
- Support Pipelined Process in CPU-to-PCI Access
- Support Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Support Memory Remapping Function for PCI master accessing
Graphical Window
o Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
- Support Asynchronous and Synchronous A.G.P. Clock
- Support 1X, and 2X Mode for A.G.P. 66/133 MHz 3.3V device
- Support Graphic Window Size from 4Mbytes to 256Mbytes
- Different arbitration policy for A.G.P. devices and 66Mhz PCI
devices.
- Translates Sequential CPU-to-A.G.P. Memory Write Cycles into
A.G.P. Bus (PCI66) Burst Cycles
- Zero Wait State Burst Cycles
- Support Pipelined Process in CPU-to-A.G.P. Access
- Support Advance Snooping for A.G.P. Master initiate system
memory access with PCI Cycles
- Support 8 Way, 16 Entries Page Table Cache to enhance A.G.P.
Read/Write Performance
- Support Both 1-Level and 2-Level GART (Graphic Address Re-
Mapping Table)
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Programmable Counters to Ensure Guaranteed Minimum Access Time
for Low Priority Request, CPU to A.G.P./and A.G.P. Master
Transaction
- Support PCI-to-PCI bridge function for memory write from 33Mhz
PCI bus to A.G.P. bus
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
- CPU-to-PCI66 Posted Write Buffer(CTAFF) with 8 DW Deep
- PCI66-to-Memory Posted Write Buffer(ATHFF) with 8 QW Deep
- A.G.P. Request Queue With the Depth of 32
- A.G.P. High Priority Write Queue with 64 QW Deep
- A.G.P. Low Priority Write Queue with 64 QW Deep
- A.G.P. High Priority Read Return Queue with 64 QW Deep
- A.G.P. Low Priority Read Return Queue with 64 QW Deep
o Fast PCI IDE Master/Slave Controller
- Bus Master Programming Interface for ATA Windows 95 Compliant
Controller
- Plug and Play Compatible
- Support Scatter and Gather
- Support Dual Mode Operation - Native Mode and Compatibility
Mode
- Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
- Support Multiword DMA Mode 0, 1, 2
- Support Ultra DMA/33
- Two Separate IDE Bus
- Two 16 DW FIFO for PCI Burst Transfers.
o Support NAND Tree for Ball Connectivity Testing
o 553-Balls BGA Package
o 0.35μm 3.3V CMOS Technology
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97
***Info:...
***Versions:...
***Features:
General
o Plug & Play 1.0A Compliant
o Support 13 IRQs, 4 DMA channels, full 16-bit addresses decoding
o Capable of ISA Bus IRQ Sharing
o Compliant with Microsoft PC97 Hardware Design Guide
o Support DPM (Device Power Management), ACPI
o Programmable configuration settings
o 24 or 14.318 Mhz clock input
FDC
o Compatible with IBM PC AT disk drive systems
o Variable write pre-compensation with track selectable capability
o Support vertical recording format
o DMA enable logic
o 16-byte data FIFOs
o Support floppy disk drives and tape drives
o Detects all overrun and underrun conditions
o Built-in address mark detection circuit to simplify the read
electronics
o FDD anti-virus functions with software write protect and FDD write
enable signal (write data signal was forced to be inactive)
o Support up to four 3.5-inch or 5.25-inch floppy disk drives
o Completely compatible with industry standard 82077
o 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps
data transfer rate
o Support 3-mode FDD, and its Win95 driver
UART
o Two high-speed 16550 compatible UARTs with 16-byte send/receive
FIFOs
o 3rd UART with 32-byte send/receive FIFO is supported for IR
function [W83977AF/AG only]
o MIDI compatible
o Fully programmable serial-interface characteristics:
- 5, 6, 7 or 8-bit characters
- Even, odd or no parity bit generation/detection
- 1, 1.5 or 2 stop bits generation
o Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Break, parity, overrun, framing error simulation
o Programmable baud generator allows division of 1.8461 Mhz and
24 Mhz by 1 to (2^16-1)
o Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps
for 24 Mhz
Infrared
o Support IrDA version 1.0 SIR protocol with maximum baud rate up to
115.2K bps
o Support SHARP ASK-IR protocol with maximum baud rate up to 57,600
bps
o Support IrDA version 1.1 MIR (1.152M bps) and FIR (4M bps) protocol
[W83977AF/AG only]
- Single DMA channel for transmitter or receiver
- 3rd UART with 32-byte FIFO is supported in both TX/RX
transmission [W83977AF/AG only]
- 8-byte status FIFO is supported to store received frame status
(such as overrun CRC error, etc.)
o Support auto-config SIR and FIR [W83977AF/AG only]
Parallel Port
o Compatible with IBM parallel port
o Support PS/2 compatible bi-directional parallel port
o Support Enhanced Parallel Port (EPP)
− Compatible with IEEE 1284 specification
o Support Extended Capabilities Port (ECP)
− Compatible with IEEE 1284 specification
o Extension FDD mode supports disk drive B; and Extension 2FDD mode
supports disk drives A and B through parallel port
o Enhanced printer port back-drive current protection
Advanced Power Management (APM) Controlling
o Power turned on when RTC reaches a preset date and time
o Power turned on when a ring pulse or pulse train is detected on the
PHRI, or when a high to low transition on PWAKIN1, or PWAKIN2
input signals
o Power turned on when PANSW input signal indicates a switch on event
o Power turned off when PANSW input signal indicates a switch off
event
o Power turned off when a fail-safe event occurs (power-save mode
detected but system is hung up)
o Power turned off when software issues a power off command
Keyboard Controller
o 8042 based with optional F/W from AMIKKEY-2, Phoenix MultiKey/42 or
customer code
o with 2K bytes of programmable ROM, and 256 bytes of RAM
o Asynchronous Access to Two Data Registers and One status Register
o Software compatibility with the 8042 and PC87911 microcontrollers
o Support PS/2 mouse
o Support port 92
o Support both interrupt and polling modes
o Fast Gate A20 and Hardware Keyboard Reset
o 8 Bit Timer/ Counter; support binary and BCD arithmetic
o 6, 8, 12, or 16 Mhz operating frequency (16 Mhz available only if
input clock rate = 14.318 Mhz)
Real Time Clock
o 27 bytes of clock, On-Now, and control/status register (14 bytes in
Bank 0 and 13 bytes in Bank 2); 242 bytes of general purpose RAM
o BCD or Binary representation of time, calendar, and alarm registers
o Counts seconds, minutes, hours, days of week, days of month, month,
year, and century
o 12-hour/ 24-hour clock with AM/PM in 12-hour mode
o Daylight saving time option; automatic leap-year adjustment
o Dedicated alarm (Alarm B) for On-Now function
o Programmable delay-time between panel switch off and power supply
control
o Software control power-off; various and maskable events to activate
system Power-On
o System Management Interrupt (SMI ) for panel switch power-off event
General Purpose I/O Ports
o 14 programmable general purpose I/O ports; 6 dedicate, 8 optional
o General purpose I/O ports can serve as simple I/O ports, interrupt
steering inputs, watching dog timer output, power LED output,
infrared I/O pins, general purpose address decoder, KBC control I/O
pins.
Package
o 128-pin PQFP
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
*General Sources:...
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