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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*OPTi...
**82C822 PCIB (VLB-to-PCI bridge) c:94
***Notes:...
***Info:
OPTi's 82C822 VESA local bus to PCI Bridge (PCIB) chip is a high
integration 208-pin PQFP device designed to work with VESA VL bus
compatible core logic chipsets. The 82C822 PCIB provides interface to
the high performance PCI bus and is fully compliant to the PCI Version
2.0 specification. The 82C822 requires no glue logic to implement the
PCI bus interface and hence it allows designers to have a highly
integrated motherboard with both VESA local bus and PCI local bus
support. The PCIB chip offers premium performance and flexibility for
VESA VL-based desktop systems running up to 50MHz. The 82C822 PCIB can
be used with OPTi's 82C802G core logic and 82C602 buffer chipsets to
build a low cost and power efficient 486-based desktop solution. It
also works with OPTi 82C546/547 chipset to build a high performance
PCI/VL solution based on the Intel P54C processor.
The 82C822 PCIB provides all of the control, address and data paths to
access the PCI bus from the VESA Local bus (VL bus). The 82C822
provides a complete solution including data buffering, latching,
steering, arbitration, DMA and master functions between the 32-bit VL
bus and the 32-bit PCI bus.
The PCIB works seamlessly with the motherboard chipset bus arbiter to
handle all requests of the host CPU and PCI bus masters, DMA masters,
I/O relocation and refresh. Extensive register and timer support are
designed into the 82C822 to implement the PCI specification.
The 82C822 is a true VESA to PCI bridge. It has the highest priority
on CPU accesses after cache and system memory. It generates LDEV#
automatically and then compares the addresses with its internal
registers to determine whether the current cycle is a PCI cycle. When
a cycle is identified as PCI cycle, the 82C822 will take over the
cycle and then return RDY# to the CPU. If not, the 82C822 will give up
the cycle to the local device or, in the case of an ISA slave,
generate a BOFF# cycle to the CPU. This action will abort the cycle
and allow the CPU to rerun the cycle.
The 82C822 includes registers to determine shadow memory space, hole
locations and sizes to allow the 82C822 to determine which memory
space should be local and which is located on the ISA bus. Upon access
to memory, the 82C822 can determine whether or not the cycle is a PCI
access by comparing the cycle with its internal registers.
***Versions:...
***Features:...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
*VIA...
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*Western Digital...
*Winbond...
**W83C553F System I/O Controller With PCI Arbiter c:sep95
***Info:...
***Versions:...
***Features:
High Integration PCI-ISA solution
o Optimized for lowest system cost
o Complies with PCI Revision 2.0 specification
o Universal PCI device supporting x86 and PowerPC (non-x86) modes of
operation
Nand tree on most signal pins to facilitate board level testing in PCB
manufacturing environment
Integrated PCI Bus Master IDE controller
o Dual channel Bus Master IDE for up to 4 peripherals, including hard
drives, ATAPI (IDE) CD-ROMs, tapes, etc.
o Multi-threading capability allows two simultaneous I/O processes
o Independent IDE Timing registers allow fast/slow devices on the
same cable
o Two independent DMA channels for Bus Master scatter/gather DMA
transfers across the PCI bus
o Large 64 byte DMA FIFO for zero wait state PCI burst transfers
o Support for multiword DMA Mode 1 (13.3 MB/s), Mode 2 (16.6 MB/s)
IDE drives
o PIO IDE support for Modes 0-4 disks
o Edge rate controlled outputs directly drive IDE headers
o Four byte pre-fetch and posted write buffers
o DMA channels can be re-configured for P-n-P motherboard devices
o Software and register set compatible with Intel Bus Master PCI-IDE
specification (SFF 8038i)
o Supported by existing device drivers for MS-DOS, Windows, NT 3.1,
NT 3.5x, NT4.0, OS/2 2.1, OS/2 Warp, NetWare 3.12 and 4.x**
o Recompiled PowerPC device drivers also available
>** OS/2, Novell driver by DTC
PCI Arbiter
o Supports CPU, IDE, ISA and five additional bus masters
o Programmable access windows allow fine tuning of PCI access for
each bus master
o Can be disabled on power-up via strapped pin
Power Management Break Event support for Green PC applications
Built-in Integrated Peripheral Controller (IPC) with standard PC-AT
peripherals
o Two 82C37A DMA controllers (types A, B, and F)
- 32-bit addressing allows use of alternate CPUs, such as PowerPC
- supports multiple 8-bit and 16-bit scatter/gather DMA channels
o Two 82C59A interrupt controllers
- all IRQ inputs may be programmed for edge or level sensitivity
o One 82C54 counter/timer
o Routes external PCI interrupts to a software-selectable interrupt
channel
PCI Bus Interface
o PCI Revision 2.1 compliant
o PCI clock frequencies up to 33 MHz at 5V
o Supports delayed completion for ISA cycles
o Active address decoding for internal I/O devices
o Subtractive decoding for ISA bridge, KBC and RTC
o Supports disconnection (with retry) for slow internal accesses to
improve latency
o Short PCI bus ownership when mastering to minimize overall system
latency
o Fast DMA transfers from I/O devices to PCI agents as a master
o Separate request and grant signals for ISA DMA and IDE controllers
ISA Bus Bridge
o Full implementation of a standard ISA bus
o Separate ISA and IDE data buses reduce noise and increase system
performance
o Synchronous PCI-to-ISA interface with direct drive for 5 ISA slots
XD-Bus interface
o Support for BIOS ROM or PowerPC systems boot ROM
o Support for flash EPROM
o Provides keyboard controller connections
o Provides real-time clock connections
o Provides data buffer control
Miscellaneous
o Port B support
o Port 92 support
Uses 0.6um, ultra-low power CMOS technology for Rev. E and below;
0.5um for Rev. G. Packaged in a 208-pin PQFP package
**W83628F/29D PCI TO ISA Bridge Set c98...
**W83626F/D LPC TO ISA Bridge Set <00...
**
**Multi I/O:
**W83757 SUPER I/O CHIP <92...
**W83767F ?? Multi I/O [no datasheet]
**W83777F/87F Power I/O (Multi I/O) <95...
**W83877F WINBOND I/O (Multi I/O) <96...
**W83877TF/TG/TD WINBOND I/O (Multi I/O) c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
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