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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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**UM82C852     Multi I/O For XT                                    <91
***Info:
The  Multi-I/O  chip, UM82C852  is  an  integrated  chip of  UM82C450,
UM82C11, UM82C8167. This  chip is a Multi-I/O for  PC/XT and PS2 model
30.

The   82C450  asynchronous   communications  element   (ACE)  performs
serial-to-parallel  conversion   on  data  characters   received  from
peripheral  devices or  modems, and  parallel-to-serial  conversion of
data characters transmitted by the CPU. The complete status of the ACE
can  be read  at  any time  during  functional operation  by CPU.  The
information obtained  includes the type and condition  of the transfer
operations being performed and error conditions.

The  82C11  parallel  port  provides  the user  with  a  bidirectional
parallel data  port that fully  supports the parallel  Centronics type
printer.

The 82C8167 real time clock includes an addressable real time counter,
56 bits  of static RAM with  an on chip oscillation  circuit which can
generate the 32,768 Hz time base.

The 82C852 is packaged in a 68-pin plastic leaded chip carrier.
***Versions:...
***Features:...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91
***Info:...
***Versions:...
***Features:
o   84-pin PLCC and PQFP packages
o   5V supply requirement (WD76C20) 
    3.3V supply requirement (WD76C20LV)
o   3.0V battery backup supply for the RTC and 114 byte SRAM (WD76C20) 
    2.4V battery backup supply for the RTC and 114 byte SRAM 
    (WD76C20LV)
o   Implemented in a low-power, high-performance, 1.25 micron CMOS 
    technology process
o   Floppy Disk Controller (FDC) software transparent power-down mode 
    with low standby ICC current. FOC features:
    - 256 tracks support
    - 100% software compatible with NEC 765A
    - Integrated high-performance DPLL data separator:
       - 125, 250, 300, 500 Kb/sec and 1 Mb/sec data rates
       - Option to select 150 Kb/sec FM and 300 Kb/sec MFM data 
         rates only
    - Automatic Write Precompensation:
       - Defeat option
       - Inner track value of 125 or 187 ns pin selectable
    - On chip clock generation:
       - 2 TTL clock inputs, or 
       - Single 16 or 32 MHz crystal circuit and one TTL clock input
    - Power Qualified Reset
       - Enable PQR in W076C20
       - Disable PQR in W076C20LV
    - Host interface read/write accesses compatible with 80286 
      microprocessors at speeds up to 12 MHz with 0 wait states
    - Direct floppy disk drive interface - no buffers needed
       - 48 mA sink output drivers
       - Schmitt Trigger input line receivers
    - FDC direct PC XT/AT interface compatibility
       - Floppy Control and Operations Registers on chip
       - In PC/AT mode, provides required signal qualification to DMA 
         channel
       - IBM BIOS compatible
       - Dual-speed spindle drive support
    - PS/2 type drive support
o   Real Time Clock (RTC) features:
    - Software compatible with Motorola MC146818A.
    - Internal time base and oscillator circuitry 
    - Counts seconds, minutes, and hours
    - Counts days of the week, date, month, and year
    - Time base input for 32.768 KHz square wave
    - Time base oscillator for parallel resonant crystals
    - Binary or BCD representation of time, calendar, and alarm
    - 12- or 24-hour clock with AM and PM in 12-hour mode
    - Daylight savings time option
    - Automatic leap year compensation
    - Interfaced with software as 128 RAM locations
    - 114 bytes at general purpose RAM
    - Status bit indicates data integrity
    - Bus compatible interrupt signals (IRQ)
    - Three interrupts are separately software maskable and testable:
       - Time-at-day alarm - once-per-second to once-per-day
       - Periodic interrupt rates tram 122 us to 500 ms
       - End-at-clock update cycle

**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
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