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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*Logicstar...
**SL6012 Memory Mapper for PC-AT (74LS612 compatible) <Jul87
***Info:
The SL6012 Memory Mapper is intended for use in PC-AT design. It can
expand an address bus by 4 bits. In PC-AT applications, 4 bits of the
source address are used to select 1 of 16, eight bit map
registers. These registers are normally programmed (through software)
with the starting address of each memory page. The register data is
output directly for use as the most significant bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.
As shown in Table 1 [see datasheet], the SL6012 has three modes of
operation; read, write and map. Data may be written into, or read from
the Memory Mapper when chip select CSN is low. The register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is low, data is written into a register from the data bus. When
RWN is high data is output from a Memory Mapper register to the data
bus.
The map mode of operation is selected when chip select CSN is high. In
this mode, the register data selected by the map address inputs (MA0
through MA3) will be available on the map outputs (MO0 through
MO7). Note that the map registers are addressed by either the RS
inputs or the MA inputs depending upon the operating mode. When MEN
(Map Enable) is low the map outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.
***Versions:...
***Features:...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88...
**SL9020 Data Controller <oct88...
**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Symphony...
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*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE3600/A/B/C 16/20MHz AT Chip set c:88
***Notes:...
***Info:...
***Configurations:...
***Features:
****FE3001 AT CONTROL LOGIC...
****FE3010B AT PERIPHERAL CONTROL LOGIC...
****FE3021 ADDRESS BUFFER AND MEMORY CONTROLLER...
****FE3031 AT DATA BUFFER...
**FE5300 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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