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**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?
***Info:...
***Configurations:...
***Features:...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:
***PII
None of this information has been checked against actual datasheets.

North/South    Name:                 CPU      FSB     AGP RAM
M1621/M1533    Aladdin Pro           PII      66/100  2x  2GB EDO SDRAM
M1621/M1543/C  Aladdin Pro II        PII Dual 66/100  2x  2GB EDO SDRAM
M1631/M1535D   Aladdin TNT2 (UMA)    PIII/Cel 66/100  2x  1.5GB EDO SDRAM
M1632          Aladdin Cyber Blade 2 PIII     100     2x  1.5GB EDO SDRAM 
M1641B/M1535D  Aladdin Pro 4         PIII/Cel 66/100  4x  1.5GB EDO SDRAM
M1644/M1535D+  Aladdin Cyberblade XT PIII/Cel 100/133 4x  3GB SDRAM DDD
M1644M/M1535D+ Aladdin-T Cyberblade  [same as 1644/M1535D+ but supports Tualatin]
M1651/M1535D+  Aladdin Pro 5         PIII/Cel 100/133 4x  3GB SDRAM DDR
M1651T/M1535D+ Aladdin Pro 5T        [same as M1651/M1535D+ but supports Tualatin]

"Aladdin Cyberblade" above is short for "CyberAladdin Cyberblade". All
Cyberblade chips have integrated video, as does the Aladdin TNT2.

***Athlon...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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