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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91
***Info:
The HT21 is an advanced PC/AT compatible, single-chip 80386SX/80286
design solution. This highly integrated single chip allows simple,
low cost system design options while featuring high performance, low
power consumption, and minimum board space requirements. Advanced
memory management features include support for page mode, 2 or 4-way
interleaving in both pipelined and non-pipelined modes. The LIM 4.0
hardware implementation features dual sets of 32 registers with full
context support for highest performance Optimization of extended local
memory accesses. An advanced EMS hardware write-protect option is
provided. The HT21 supports 256K and 1M DRAMs in l by 1, 1 by 4, and 1
by 9 device configurations for up to 8MB of on-board system memory. A
flexible Shadow RAM option for System and Video BIOS as well as 8-
16-bit BIOS Options adds to overall design versatility.
A complete PC/AT compatible system with advanced features may be
implemented with minimal external support logic. The HT21 performs all
CPU and peripheral support functions in a single chip. Integrated
device functions include DMA Controllers, a Memory Mapper, Timers,
Counters, Interrupt Controllers, a Bus Controller and all supporting
circuitry for PC core logic requirements. The chip also contains all
the necessary address buffers, data transceivers, memory drivers,
parity checking and supporting circuitry for a complete high
performance computer solution. An asynchronous AT Bus clock allows for
a constant 8MHz Bus clock rate for highest bus device compatibility as
defined in IEEE Spec P996. In controlled bus applications the HT21
supports up to a 12 MHz Bus Clock rate. This device is packaged in a
208-pin Plastic Quad Flat Pack combining several external buffers into
this space saving solution.
***Configurations:...
***Features:...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C110 Combination I/O chip ?
***Info:
The VL82C110 Combination I/O chip replaces several of the commonly
used peripherals found in PC/AT-compatible computers. The VL82C110
contains a 765A compatible floppy disk controller with a digital data
clock separator, writ precompensation logic and the necessary control
registers. It also contains two 16C450 compatible UARTs, a Centronics
compatible printer port, and an internal PMU (power management unit)
which is useful in applications where low power consumption is
essential. Additionally, a PLL clock circuit is included to provide
one of seven of the commonly used CPU clock frequencies. This 100-pin
chip allows designers to implement a very cost-effective, minimum chip
count motherboard containing functions that are common to virtually
all PCs.
The internal PMU provides a Sleep output which OS asserted via
automatically after a programmable time delay period of inactivity in
any of the major on-chip functions. Conversely, the sleep output will
be de-asserted when any activity is detected to any of the major
on-chip functions.
The on-chip UARTs are 100% software compatible with the VL16C450 ACE.
The bidirectional parallel port provides a PS/2 software compatible
interface between a Centronics-style printer and the VL82C110. Direct
drive is provided so that all that is necessary to interface to the
line printer is a resistor-capacitor network. The bidirectional
feature (option) is software programmable for backwards PC/AT-
compatibility.
The on-chip disk controller OS 100% compatible to the industry
standard 765A. The internal digital data separator is capable of
operating up to a 500 kb/s data rate. The Controller also implements
all of the DP8473 disk controller functions.
The necessary signals are provided to implement the Integrated Drive
Electronics (IDE) interface.
A 24 MHz oscillator is included for UART baud rate generation and the
floppy disk controller clock, It is also used to generate, via
software control, a 20, 25, 32, 40, 50, 66 or 80 MHz output which can
be used as a CPU input clock. This feature may be disabled at power-up
reset time.
Software configurable registers are provided to enable and disable
major blocks, assign addresses, and control other functions within the
VL82C110.
***Versions:...
***Features:...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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