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**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?
***Info:...
***Configurations:
M1541/M1542 System Controller
M1533/M1543 PCI-to-ISA Bus Bridge
M1541 + M1533
M1541 + M1543
M1542 + M1533
M1542 + M1543
See the M1531 section for details on the M1533.
The datasheet is very confusing as it does not state how the terms
M1531, M1532, Aladdin V and Aladdin V+ relate to each other. According
to:
http://pclinks.xtreemhost.com/chipsets_pentium.htm
The Aladdin V and Aladdin V+ names are both associated with the M1541.
The M1541 has 5 revisions, A thru E. The M1542 part number is assoc-
iated with revision F onwards. The main difference with the M1542 is
that it now can cache 512MB of RAM, instead of only 128MB. The diff-
erence between the Aladdin V and Aladdin V+ is that the V+ officially
supports a 100 MHz bus, the V only 83.3 MHz.
However, none of this information can be derived from the datasheets
used to write the info and features section.
***Features:...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor (735\90, 810\100) to form a CPU Cache chip set
designed for high performance servers and function-rich desktops. The
high-speed interconnect between the CPU and cache components has been
optimized to provide zero-wait state operation. This CPU Cache chip
set is fully compatible with existing software, and has new data
integrity features for mission critical applications.
The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82497 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82492 is a customized high-performance SRAM that supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82492, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C541/543 Lynx c95
***Notes:...
***Basics:...
***Info:...
***Configurations:...
***Features:...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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