[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C521/522 Lynx/M ?
***Info:
The VL82C520 Lynx/M chipset is VLSI's system solution optimized for
the expanding mobile Pentium market. Carrying forward VLSI's mobile
strategy and leveraging successful desktop innovations to offer a
complete solution, Lynx/M leaps forward and integrates the system
controller into a single Ball Grid Array (BGA) package. Included in
the Lynx/M solution is a PCI "Super I/O" controller that integrates
all the standard mobile peripherals. The Lynx/M offers a total
solution compatible with the Common Architecture industry standard
implementing highly efficient DDMA (Distributed DMA), Serial IRQ, and
features for primary PCI hot docking using a Common Architecture
compatible PCI to PCI bridge in the docking station.
Lynx/M System Controller; VL82C521
Packaged in a space-efficient low-profile 352 BGA, the Lynx/M System
Controller is the heart of the solution. BGA packaging allows
integrating functions usually partitioned into multiple packages. the
integrated functions include a 66Mhz CPU interface, 3.3V mobile PCI
2.1 compliant bus controller, 64-bit SDRAM, EDO, and FPM DRAM
controller with nine-deep fast access smart write-buffers, on-board L2
256KB write-back cache controller, and VLSI's WATTSmart power
management control. The DRAM interface provides drive for up to 24
memory devices thereby eliminating the need for external
drivers. Also, selecting SDRAM provides the opportunity to implement a
high performance system without an L2 cache.
Lynx/M Peripheral Controller; VL82C522
The Lynx/M chipset also includes a PCI Super I/O device, the Lynx/M
Mobile Peripheral Controller (MPC). This device, also packaged in a
low-profile 352 BGA, integrates a PCI 2.1 compliant bus interface, a
fully buffered Bus Mastering IDE controller, an '077 floppy disk
controller, Enhanced Capabilities Port (ECP), two 16550 UARTs with
modem functionality, an SMB/I2C bus, an IrDA 1.1 compatible Fast
Infrared communications port with ASK functionality, a Real-Time
Clock, two pulse-width modulator outputs (PWM), and a 33MHz 8052
microcontroller. Two on-board PLLs with buffering provide all the
required system clocks from only two crystal inputs, 14.318MHz and
32KHz.
A sub-ISA bus supporting 8- or 16-bit I/O or DDMA transfers, and ISA
Bus Mastering supports audio devices. Additionally, eight positive PCI
address decodes provide support to Sub-ISA peripherals.
The 8052 provides the keyboard controller functionality with built-in
scan for matrix keyboards and system boot controller functionality to
completely wake up any part or all of the system from any level of
suspend. The wake-up event can be a system event, timer, or any key
depression on the keyboard. The MPC also provides up to 25 GPIO pins
with expansion capabilities to provide flexible control of system
components.
Singular ROM architecture enabled by the integrated 8052 keyboard
controller saves both PCB space and cost by permitting a solitary ROM,
Flash, or SRAM device to be used for keyboard, graphics and system
BIOS.
WATTSMART Power Management
Incorporated in the Lynx/M chipset, the WATTSmart is a System
Management Mode-based power management system. WATTSmart includes
multiple system event monitoring, a watchdog timer, System Management
Interrupt (SMI) generation, multiple I/O traps, CPU Stop Clock
control, and provides three general purpose system Management I/O pins
(SMIOs) for control and monitoring of external devices.
Virtually all activity resources are available as speed up events and
to generate SMIs. SMIs can be generated by activity or after a period
of inactivity. An SMI that is generated from activity is generally for
a powered-down device, and the SMM handler can restore the device to
normal operation. An SMI from activity can also be used to resume the
system, start the clocks, etc.
Background
Lynx/M incorporates functions from previous desktop and mobile
chipsets. Baselinning from proven core system blocks and modifying to
reflect new market requirements allows VLSI to meet the Time-To-Market
expectations while minimizing risk.
Utilizing high-pin count BGA packaging allows Lynx/M to reduce board
space requirements by greater than 45%. this allows room on the PCB
for additional functionality while reducing the complexity of
multi-layer system boards.
Accessing VLSI's internal fab technology allows Lynx/M a path to an
advanced 0.6um CMOS process thereby achieving a true 3.3V system
without performance trade-offs.
***Configurations:...
***Features:
o Support for Pentium and Pentium-class CPUs
o 64-bit wide SDRAM, EDO, and FPM DRAM controller
o Nine-deep, 64-bit fast-access smart write buffers
o Fully PCI 2.1 compliant, 33MHz, synchronous or asynchronous, high
performance (120 MB/s) PCI bus with full concurrency to support
high bandwidth multi-media
o Flexible L2 write-back cache controller supporting 3-1-1-1-1-1-1-1
burst cycles
o Highly integrated chipset in low-profile BGA packages
o Active thermal feedback (ATF) for closed-loop thermal control of
the CPU
o PCI bridge support for high-performance primary PCI hot docking
o Common Architecture Serial Bus minimizes docking connector pin
count
o SMB/I2C system management bus improves battery monitoring
o Singular ROM for keyboard, System and graphics BIOS
o Full 2 channel Bus Mastering IDE controller
o Integrated '077 FDC
o Two 16550 UARTs
o 8052 keyboard controller with built-in scan for matrix keyboards and
boot controller functionality
o system clocks from power-managed PLLs with on-board buffering for
distribution
o Two PWMs to provide LCD backlight and contrast control
o Parallel port with PS2, EPP and ECP extensions
o Built-in IrDA 1.1 Fast Infrared communications port
o Multiple VCC rails and on-board level shifters to provide inder-
pendent power-down and true 5.0 Vdc peripheral support
o Support for three PS2 ports
o Real-Time Clock with CMOS
o 25 GPIO pins with expansion
o Built-in Sub-ISA bus for 16-bit DMA ISA Master audio device
o Supports 3.3V and 0V suspend with multiple resume events, I/O
trapping, and audio 0V suspend/resume
o Bus Keeper I/Os to reduce battery drain in suspend mode
o Supports shut-down option for CPU core power during powered
suspend to maximize battery life
o Supports CPU clock division emulation to effectively reduce CPU
clock frequency
o Plug-N-Play support
o Compliant with Microsoft recommendations for Win '95
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved