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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**5595 Pentium PCI System I/O <12/24/97
***Notes:...
***Info:...
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**950 LPC I/O <07/16/99...
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*VIA...
*VLSI...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?
***Info:
The VL82C3216 Bus Expanding Controller (BANC) Cache with Write Buffer
is specifically designed to provide a high-performance, low-cost
solution for interfacing 386SX PC/AT-compatible chip sets to 386DX,
Am386DXL, AM386DXLV, 486DX, 486SX, or compatible processors. The
designs may be entirely new systems or upgrades to existing
ones. Power management features also make this device ideal for laptop
computers or other battery operated systems. The performance is
achieved through the use of a write buffer structure, an external
second level cache, prediction algorithms, and maximizing the internal
first level cache of the i486, if used.
The high level of integration is entered on the VL82C3216. It
controls all functions between the host processor bus and the 386SX
local bus. in addition the the write buffer and second- and
first-level cache controls, the VL82C3216 contains prediction and
burst mode algorithms that take full advantage of the page mode design
of existing 386SX system architecture. Through the use of pipelined
page mode accesses to system memory, the VL82C3216 bursts data to and
from memory at rates of up to 25 MB per second. This provides 32-bit
memory performance at 16-bit memory costs.
***Versions:...
***Features:...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
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