[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?
***Info:...
***Configuration:...
***Features:
o Three chip, PC/AT-compatible chip set capable of use in 80386DX-
based systems from 16 to 33 MHz
o Two 128-lead and one 160-lead plastic quad flatpacks, 1.0 and 1.5
micron CMOS
o Memory control of one to four banks of 32-bit DRAM using 256K. 1M
or 4M components allowing 64M bytes on system board
o Two-/four-way page mode interleaving or direct access on system
board memory
o Programmable DRAM timing parameters
o Remap option allows logical reordering of system board DRAM banks
o Staggered system board refresh optionally decoupled from slot bus
refresh
o Built-in "sleep" mode features, including use of slow refresh
DRAMs in power critical operations
o Hardware supports full EMS 4.0 spec over entire 64M byte memory
map
o DMA expanded to allow transfers over 64M byte range
o Shadow RAM support in 16K increments
o Support for 80387DC and Weitek 3167 numerical coprocessors
o Internal switching and programmable CPU clock support for PC/AT-
compatible and "turbo" modes
o Asynchronous or synchronous slot bus with "Bus Quiet" mode
o Built-in real-time clock and scratchpad RAM
o Additional 64 bytes of battery backed RAM in RTC
o Supports 8- or 16-bit wide BIOS ROMs
o Cache support for posted writes
o In-circuit test modes
o Support for the VL82C335 Cache Controller is provided by the
VL82C330A
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C310 SCAMP-LT ?...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?
***Info:
The VL82C425 Cache Controller provides a low-cost direct map,
look-aside write-back cache option for use with the VL82C486 System
Controller. It supports from 64 KB to 1 MB cache sizes. It can cache
from the first 8 MB to the first 256 MB of on-board DRAM, depending on
the cache size and tag option selected. the cache line size is 16
bytes (four double words).
one or two 32-bit wide banks of asynchronous cache SRAM may be used to
hold the data. Increased read performance is obtained by using two
banks which allow interleaved accesses during burst read cycles.
only one 8-bit or 9-bit (optional) tag SRAM is required to hold the
upper memory address bits and the dirty bit. The number of tag SRAM
locations required is equal to the size of the data cache (in bytes)
divided by 16.
***Versions:...
***Features:...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved