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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**?????  (Profusion)    c:99...
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*VLSI...
**VL82C386-SET     TOPCAT 386DX PC/AT-Compatible Chip Set            ?
***Info:
The TOPCAT 386DX  chip set from VLSI Technology, Inc.,  is a very high
integration chip set  for use in the design  of PC/AT-compatible based
systems.    This   chip  set   is   intended   for  use   in   80386DX
microprocessor-based systems with clock speeds form 16 to 33 MHz.

The  TOPCAT 386DX  chip  set  provides design  engineers  with a  very
flexible, high-  performance, low-cost  board design solution  for IBM
PC/AT-compatible desktop, laptop, portable, and hand-held computers.

The  TOPCAT 386DX  three-device chip  set has  been designed  with the
highest  integration  consistent  with economic  and  reliable  system
design. It provides  a complete board design using  only 10 non-memory
devices including the microprocessor.

VLSI's The TOPCAT 386DX chip set was designed with seven goals.
o   lowest system board cost
o   Smallest board area requirement
o   highest performance in both cached and non-cached systems
o   single board design for:
    - 16 to 33 MHz operation
    - Cache or non-cache
    - 1M byte to 64M byte memory using 256K, 1M, and 4M bit DRAM
    - Laptop or desktop applications
o   Full hardware LIM EMS 4.0 support for the highest possible 
    performance
o   Built-in, in-circuit test modes for easy board level testing.
o   the VL82C330A interfaces to the VL82C335 "look-aside" Cache 
    Controller

with  VLSI's TOPCAT  386DX  chip set,  you  can be  assured that  your
high-performance system design needs are met.

***Configuration:...
***Features:...
**VL82C386sx-SET   TOPCAT 286/386SX PC/AT-Compatible Chip Set        ?...
**VL82C310         SCAMP-LT                                          ?...
**VL82C311         SCAMP-DT                                          ?...
**VL82C311L        SCAMP-DT 286                                      ?...
**VL82C312         SCAMP Power Management Unit (PMU)                 ?...
**VL82C315A        SCAMP II, Low-Power Notebook Chipset              ?...
**VL82C322A        SCAMP II, Power Management Unit (PMU)             ?...
**VL82C316         SCAMP II, PC/AT-Compatible System Controller      ?...
**VL82C323         SCAMP II, 5 Volt Power Management Unit (PMU)      ?...
**VL82C380         Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325             VL82C386SX System Cache controller            ?...
**VL82C335             VL82C386DX System Cache ctrl. [no d.sheet]    ?...
**VL82C315A/322A/3216  Kodiak 32-Bit Low-Voltage Chip Set            ?...
**VL82C420/144/146     SCAMP IV [no datasheet, some info]          c93...
**VL82C480         System/Cache/ISA bus Controller                   ?...
**VL82C481         System/Cache/ISA bus Controller                 c92...
**VL82C486         Single-Chip 486, SC486, Controller                ?...
**VL82C425         486 Cache controller                              ?
***Info:
The  VL82C425  Cache  Controller   provides  a  low-cost  direct  map,
look-aside write-back  cache option for  use with the  VL82C486 System
Controller. It supports from  64 KB to 1 MB cache  sizes. It can cache
from the first 8 MB to the first 256 MB of on-board DRAM, depending on
the cache  size and  tag option  selected. the cache  line size  is 16
bytes (four double words).

one or two 32-bit wide banks of asynchronous cache SRAM may be used to
hold the  data. Increased  read performance is  obtained by  using two
banks which allow interleaved accesses during burst read cycles.

only one  8-bit or 9-bit (optional)  tag SRAM is required  to hold the
upper memory  address bits and the  dirty bit. The number  of tag SRAM
locations required is  equal to the size of the  data cache (in bytes)
divided by 16.

***Versions:...
***Features:...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
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