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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
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*UMC...
**Other chips:
***Video:...
***Disk:...
***Peripheral:...
***Other:
UM3750A         Programmable 12-bit Encoder/Decoder
UM6502/07/12    8-bit Microprocessor 1,2,3,4 MHz Versions
UM6502E         8-bit Microprocessor 1,2,3,4 MHz Versions
UM8048/35/49/39 Microcontroller
UM8051/31       Microcontroller
UM74HCT590      8 bit Binary Counter with Output Registers
UM74HCT646      Octal Bus Transceiver and Register

UM2332/UM2333/UM2364  Mask ROM 
UM2366/A              Mask ROM
UM23128/A             Mask ROM
UM23256/A             Mask ROM
UM2147/UM2148/UM2149  SRAM
UM6104/UM6104-1       SRAM
UM6114/UM6116-2/-3/-4 SRAM
UM6116-5/UM6164       SRAM
UM6167/UM6168         SRAM

UM9001/UM9003AF Network?
UM9007F/UM9008  Network?
UM9009          Network?
UM9017F/UM9018  Ethernet
UM9026          Fast Ethernet
UM9090          Network?


*Unresearched:...
*VIA...
*VLSI...
**VL82C425         486 Cache controller                              ?
***Info:
The  VL82C425  Cache  Controller   provides  a  low-cost  direct  map,
look-aside write-back  cache option for  use with the  VL82C486 System
Controller. It supports from  64 KB to 1 MB cache  sizes. It can cache
from the first 8 MB to the first 256 MB of on-board DRAM, depending on
the cache  size and  tag option  selected. the cache  line size  is 16
bytes (four double words).

one or two 32-bit wide banks of asynchronous cache SRAM may be used to
hold the  data. Increased  read performance is  obtained by  using two
banks which allow interleaved accesses during burst read cycles.

only one  8-bit or 9-bit (optional)  tag SRAM is required  to hold the
upper memory  address bits and the  dirty bit. The number  of tag SRAM
locations required is  equal to the size of the  data cache (in bytes)
divided by 16.

***Versions:...
***Features:...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...