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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**Other chips:
***Video:...
***Disk:

UM8272A/A-4   Floppy Disk Controller 4, 8 MHz Versions
UM82C776      ISA bridge
UM82C865F     Super I/O (May be compatible with SMC37C665GT)
UM82C862      ISA IDE controller
UM82C863F     VLB IDE controller
UM82C871F     VLB IDE controller 1 port
UM83C001      Hard Disk Controller For PC/XT H.D.C
UM83C002      RAM Buffer Controller
UM83C003      Hard Disk Controller Interface For PC/XT MFM H.D.C.
UM83C004      Hard Disk Controller Interface For PC/XT MFM/RLL H.D.C.
UM83C021      Hard Disk Controller For PC/AT H.D.C.
UM83C022      AT HDC Interface For PC/AT H.D.C.
UM8326/B      Floppy Disk Data Separator (FDDS) 4, 8 MHz Versions
UM8329/T/B/BT Floppy Disk Controller
UM8388        Single-Chip Floppy Disk Controller Special Design For IBM PC
UM8397        Single-Chip Floppy Disk Controller Design For IBM PC XT
UM8398        Single-Chip Floppy Disk Controller Special Design For IBM PC
UM8660        Super I/O?
UM8670        Super I/O
UM8672        EIDE controller VLB 2 ports
UM8672F       VLB IDE controller, LBA support
UM8673F       PCI EIDE controller
UM9228-1      Floppy Disk Controller

***Peripheral:...
***Other:...
*Unresearched:...
*VIA...
*VLSI...
**VL82C425         486 Cache controller                              ?
***Info:
The  VL82C425  Cache  Controller   provides  a  low-cost  direct  map,
look-aside write-back  cache option for  use with the  VL82C486 System
Controller. It supports from  64 KB to 1 MB cache  sizes. It can cache
from the first 8 MB to the first 256 MB of on-board DRAM, depending on
the cache  size and  tag option  selected. the cache  line size  is 16
bytes (four double words).

one or two 32-bit wide banks of asynchronous cache SRAM may be used to
hold the  data. Increased  read performance is  obtained by  using two
banks which allow interleaved accesses during burst read cycles.

only one  8-bit or 9-bit (optional)  tag SRAM is required  to hold the
upper memory  address bits and the  dirty bit. The number  of tag SRAM
locations required is  equal to the size of the  data cache (in bytes)
divided by 16.

***Versions:...
***Features:...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...