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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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*UMC...
**UM82C852     Multi I/O For XT                                    <91
***Info:...
***Versions:...
***Features:
o   Supports game port
o   Supports 2nd serial port
o   Centronics printer interface
o   Independent control of transmit, receive, line status and data set 
    interrupts
o   Individual modem control signals
o   Programmable serial interface characteristics:
    — 5, 6, 7 , or 8 bit characters
    — Even, odd or no-parity bit generation and detection
    — 1, 1-1/2, or 2 stop bit generation
o   Milliseconds through month counters for real time clock 56 bits of
    RAM 
    with comparator for comparing the real time counter to the RAM 
    data
o   POWER DOWN input that disables all inputs and outputs
o   Disables the chip from the reset of the system for standby low 
    power operation by use of a POWER DOWN input
o   32,768 Hz crystal for real time clock
o   Four-year calendar (no leap year)
o   24-hour clock

**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
**VL82C425         486 Cache controller                              ?
***Info:
The  VL82C425  Cache  Controller   provides  a  low-cost  direct  map,
look-aside write-back  cache option for  use with the  VL82C486 System
Controller. It supports from  64 KB to 1 MB cache  sizes. It can cache
from the first 8 MB to the first 256 MB of on-board DRAM, depending on
the cache  size and  tag option  selected. the cache  line size  is 16
bytes (four double words).

one or two 32-bit wide banks of asynchronous cache SRAM may be used to
hold the  data. Increased  read performance is  obtained by  using two
banks which allow interleaved accesses during burst read cycles.

only one  8-bit or 9-bit (optional)  tag SRAM is required  to hold the
upper memory  address bits and the  dirty bit. The number  of tag SRAM
locations required is  equal to the size of the  data cache (in bytes)
divided by 16.

***Versions:...
***Features:...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...