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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**????? (Profusion) c:99...
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*VLSI...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?
***Info:
The VL82C316 is a true single chip AT, high-performance controller for
386SX-based PC/AT systems. The VL82C316 is intended primarily for low-
power applications requiring a high degree of integration (e.g.
notebooks). However, the VL82C316 is also an excellent choice for
high- integration, low-cost desktop systems running up to 33 MHZ.
The VL82C316 includes the dual 82C37 DMA controllers, dual 82C59A
programmable interrupt controllers, 82C54 programmable interval timer,
82284 clock and ready generator, 82288 bus controller, 8042 keyboard
controller, and 146818A-compatible real-time clock. Also included is
the logic for SMM (system Management Mode) control, address/data bus
control, memory control, shutdown, refresh generation and refresh/DMA
arbitration.
The controller also includes the following:
o AMD and Cyrix compatible SMM and I/O Break interface
o Complete ISA bus interface logic
o Integrated power management features
o Supports slow and self-refresh DRAM
o Memory/refresh controller
o Port B and NMI logic
o Bus steering logic
o Turbo Mode control logic
o Optional parity checking logic
o Optional parity generation logic
The VL82C316 supports 387SX-compatible numeric coprocessors including
versions that support slow and stop clock operation.
The memory controller logic is capable of accessing up to 16 MB. There
can be up to four banks of 256K, 1M, or 4M attached in the system or
eight banks of 512K x 8 DRAMS. The VL82C316 can drive the full
compliment of DRAM banks without external buffering. It features
Built-in Page Mode operation. This, along with two-way interleaving
allow the PC designer to maximize system performance using low-cost
DRAMs. Support is also included for zero, one, or two wait state
operation of system DRAM.
Shadowing features are supported on 16k boundaries between C0000h and
DFFFFh, and on 32K boundaries between A0000h and BFFFFh, and between
E0000h and FFFFFh. Simultaneous shadowed ROM, and direct system board
access is possible in a non-overlapping fashion throughout this memory
space. Control over four access options is provided. The options are:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.
The VL82C316 handles system board refresh directly and controls the
timing of slot bus refresh. Refresh is performed in the standard
PC/AT-compatible Mode where on- and off-board refreshes are performed
synchronously. Refreshes are staggered to minimize power supply
loading and attenuate noise on the VDD and ground pins. In the
VL82C316, refresh can be programmed to support CAS-before-RAS refresh
operation or standard RAS-only refresh operation, self-refresh, or no
refresh operation. The VL82C316 supports the PC/AT standard refresh
period of 15.625 plus 125 us or 250 us slow refresh options. When the
Suspend Mode is active, the real-time clock's 32 kHz oscillator is
used as the timing reference for absolute minimum power
dissipation. Self-refresh is possible only in the Suspend Mode. DRAM
accesses are not possible in this mode of operation. When
self-refresh is active, it is only enabled when the Suspend Mode is
also active. Otherwise, CAS-before-RAS refresh is used.
A 146818A-compatible real-time clock (RTC) is provided that supports
battery voltages down to 2.4 volt standard. It also includes 128 extra
battery-backed RAM locations (178 total) for operating system and
power-management support. The base address of the RTC is
programmable, but defaults to the PC standard address. the hardware
supports an external RTC. It may be used with the internal RTC or by
itself by disabling the internal RTC.
An internal keyboard controller replaces the standard 8042 required in
a standard PC environment. It provides a keyboard and PS/2 mouse
interface. As an option, the internal keyboard controller can be
disabled allowing use of an external controller.
The 387SX is supported. A software coprocessor reset does not leave a
387SX in the same state as does the reset of a 287. The VL82C316 can
be programmed to disable these software resets if problems arise.
The interrupt controller logic consists of two 82C509A megacells with
eight interrupt request lines each for a total of 16 interrupts. The
two megacells are cascaded internally and two of the interrupt request
inputs are connected to internal circuitry allowing a total of 13
external interrupt requests. There is a special programmable logic
included in the VL82C316 which allows glitch-free inputs on all the
interrupt request pins.
The interval timer includes one 82C54 counter/timer megacell. the
counter/timer has three independent 16-bit counters and six
programmable counter modes.
The DMA controllers are 82C37A compatible. The DMAs control data
transfers bet- ween an I/O channel and on- or off-board memory. DMA
can transfer data over the full 16 MB range available. There are
internal latches provided for latching the middle address bits output
by the 82C37A megacells on the data bus, and 74LS612 memory mappers
are provided to generate the upper address bits. An optional low-
power DMA mode is available. in this mode, the DMA clocks are stopped
except when DMA accesses are in progress.
The VL82C316 can be programmed for asynchronous or synchronous
operation of the AT bus.
The VL82C316 also performs all the data buffer control functions
required. Under the control of the CPU, the VL82C316 chip routes data
to and from the CPU's D bus and the slots (SD bus). The parity is
checked for D bus DRAM read operations. The data is latched for
synchronization with the CPU. Parity OS generated for all data written
to the D bus. The parity function may be optionally disabled except
when 512K x 8 DRAM memory maps are used. In this case, parity is not
an available option.
***Configurations:...
***Features:...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?
***Basics:...
***Info:
The VL82C486 is a Single-Chip High Performance Controller for 486- and
486SX/487SX- based PC/AT systems.
The VL82C486 includes the dual 82C37A DMA controllers, dual 82C59A
programmable int- errupt controllers, 82C54 programmable interval
timer, 82284 clock and ready gener- ator, 82288 bus controller and the
logic for address/data bus control, memory cont- rol, shutdown,
refresh generation and refresh/DMA arbitration.
The VL82C486 Controller is designed to perform in 486DX- or
486SX/487SX-based PC/AT- compatible systems running up to 33 MHz. The
VL82C486 replaces the following devices on the motherboard:
o Two 82C37A DMA controllers
o Two 82C59A interrupt controllers
o 82C54 timer
o 74LS612 memory mapper
o 82284 clock generator and ready interface
o 82288 bus controller
The controller also includes the following:
o Memory/refresh controller
o Port B and NMI logic
o Bus steering logic
o Turbo Mode control logic
o Parity checking logic
o Parity generation logic
o Support for Weitek numeric coprocessors.
The memory controller logic is capable of accessing up to 64 MB. There
can be up to four banks of 256K, 1M, or 4M DRAMs used in a system. The
VL82C486 can drive four banks without external buffering. Built-in
Page Mode operation and up to four-way interleaving allows the PC
designer to maximize system perform- ance using low-cost
DRAMs. Programmable DRAM timing is provided for RAS pre- charge,
RAs-to-CAS delay, and CAS pulse width.
Shadowing features are supported on 16K boundarys between A0000h and
FFFFFh (640 KB to 1 MB). simultaneous use of shadowed ROM and direct
system board access is possible in a non-overlapping fashion
throughout this memory space. Control over four access options is
provided:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.
A special mode is supported for erasing and programming flash memories
for the case where such devices are used as the BIOS ROMs.
Three special programmable address regions are provided. The fast-bus
clock reg- ion allows accesses to certain memory regions at a faster
ISA bus clock rate for fast on-board or off-board devices. A
Non-Cacheable Region and/or a Write-Pro- tected Region may be defined
by a set of six registers that allow memory in the region 640 KB to 1
MB to be marked as non-cacheable and/or write-protected in increments
of 16 KB. A further set of registers allows a memory range anywhere in
the first 64 MB of memory to be marked as a DRAM region, an ISA bus
region, or a local bus region, either cachable or non-cacheable in
increments of 2 KB. 64 KB, or 1 MB.
Further support for devices that reside on the 486 local bus is
provided through use of the -LBA (Local Bus Access) input, which
deselects the VL82C486 during CPU cycles. Also, a memory range
anywhere in the first 64 MB of memory can be program- med via the
internal Mapping Registers to make the VL82C486 access a local bus
dev- ice as a 486 bus memory device during DMA or Master Mode
transfers.
The VL82C486 handles system board refresh directly ans also controls
the timing of slot bus refresh. Refresh may be performed in
Synchronous, Asynchronous or Decoupled Mode. In the Synchronous Mode,
slot bus and on-board DRAM refresh cycles proceed simultaneously and
all memory cycles are held until both have completed. The Async-
hronous Mode allows in- and off-board refreshes to be initiated
simultaneously, but to complete asynchronously, allowing sooner access
to DRAM. In the Decoupled Mode, a separate refresh counter is used for
slot bus refresh, allowing on-board DRAM and system refreshes to
proceed independently, with DRAM refreshes initiated during bus idle
cycles. CAS-before-RAS refresh is also supported. Refreshes are
staggered to minimize power supply loading and attenuate noise on the
VDD and ground pins. The VL82C486 supports the standard PC/AT refresh
period of 15.625 us as well as 125 us.
Support for write-through cache controllers is provided through the
use of a -MISS pin to detect cache-hits and cache-misses.
The interrupt controller logic consists of two 82C59A megacells with
eight inter- rupt request lines each for a total of 16 interrupts. The
two megacells are cascaded internally and two [sic] of the interrupt
request inputs are connected to internal circuitry allowing a total of
13 external interrupt requests. There is special progr- amable logic
included in the VL82C486 which allows deglitching of inputs on all the
interrupt request pins.
The interval timer includes one 82C54 counter/timer megacell. The
counter/timer has three independent 16-bit counters and six
programmable counter modes.
The DMA controllers are 82C37A compatible. Each controls data
transfers between an I/O channel and on- or off-board memory. DMA can
transfer data over the full 64 MB range available. there are Internal
latches provided for latching the middle address bits output by the
82C37A megacells on the data bus, and the 74LS612 memory mappers are
provided to generate the upper address bits.
The VL82C486 can be programmed to generate the ISA bus timing from the
CPU clock oscillator or a separate asynchronous oscillator.
The VL82C486 also performs all the data buffer control functions
required for a 486XX processor-based PC/AT system. Under the control
of the CPU, the VL82C486 routes data to and from the CPU's D bus, the
internal XD bus, and the slots (SD bus). During CPU ISA bus reads, the
data is latched for synchronization with the CPU. Parity is checked
for D bus DRAM read operations. The chip does not generate parity for
CPU writes to DRAM.
***Configurations:...
***Features:...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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