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*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C822 PCIB (VLB-to-PCI bridge) c:94
***Notes:...
***Info:
OPTi's 82C822 VESA local bus to PCI Bridge (PCIB) chip is a high
integration 208-pin PQFP device designed to work with VESA VL bus
compatible core logic chipsets. The 82C822 PCIB provides interface to
the high performance PCI bus and is fully compliant to the PCI Version
2.0 specification. The 82C822 requires no glue logic to implement the
PCI bus interface and hence it allows designers to have a highly
integrated motherboard with both VESA local bus and PCI local bus
support. The PCIB chip offers premium performance and flexibility for
VESA VL-based desktop systems running up to 50MHz. The 82C822 PCIB can
be used with OPTi's 82C802G core logic and 82C602 buffer chipsets to
build a low cost and power efficient 486-based desktop solution. It
also works with OPTi 82C546/547 chipset to build a high performance
PCI/VL solution based on the Intel P54C processor.
The 82C822 PCIB provides all of the control, address and data paths to
access the PCI bus from the VESA Local bus (VL bus). The 82C822
provides a complete solution including data buffering, latching,
steering, arbitration, DMA and master functions between the 32-bit VL
bus and the 32-bit PCI bus.
The PCIB works seamlessly with the motherboard chipset bus arbiter to
handle all requests of the host CPU and PCI bus masters, DMA masters,
I/O relocation and refresh. Extensive register and timer support are
designed into the 82C822 to implement the PCI specification.
The 82C822 is a true VESA to PCI bridge. It has the highest priority
on CPU accesses after cache and system memory. It generates LDEV#
automatically and then compares the addresses with its internal
registers to determine whether the current cycle is a PCI cycle. When
a cycle is identified as PCI cycle, the 82C822 will take over the
cycle and then return RDY# to the CPU. If not, the 82C822 will give up
the cycle to the local device or, in the case of an ISA slave,
generate a BOFF# cycle to the CPU. This action will abort the cycle
and allow the CPU to rerun the cycle.
The 82C822 includes registers to determine shadow memory space, hole
locations and sizes to allow the 82C822 to determine which memory
space should be local and which is located on the ISA bus. Upon access
to memory, the 82C822 can determine whether or not the cycle is a PCI
access by comparing the cycle with its internal registers.
***Versions:...
***Features:...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C480 System/Cache/ISA bus Controller ?
***Info:...
***Configurations:...
***Features:
o Fully compatible with 486-based ISA bus systems
o Power-on reset option selects various operational modes
o Up to 40 MHz CPU operation
o Replaces the following peripheral logic on the motherboard:
- Two 82C37A DMA controllers
- 74LS612 memory mappers (extended to support 64 MB)
- Two 82C59A interrupt controllers
- 82C54 timer
- 82284 clock generator and ready interface
- 82288 bus controller
o Memory controller features include:
- Up to 64 MB system memory
- 256K, 1M or 4M DRAM
- Double-sided SIMMs
- Page Mode DRAM access
- Two-way interleave support
- Programmable RAS#/CAS# timing
- Burst read and write support
- Parity generation/checking for on-board DRAM
- Staggered RAS# refresh
o Supports:
- One to four banks 32 bits wide
- 8- or 16-bit wide BIOS ROM
- shadow RAM in the 640K-1M area
- Asynchronous ISA bus operation up to 16 MHz
- Relocation of slot ROMs
- Access to devices residing on the local bus
- Weitek 4167 numeric coprocessor
o 0.8-micron CMOS technology
o 208-lead MQFP (metric quad flat pack)
o Includes:
- Memory/refresh controller
- Port A, B, and NMI logic
- Bus steering logic
- Turbo control
- hidden refresh
- Three-stateable outputs for board testing
o Selectable slow DRAM refresh saves power
o On-chip write-back cache controller:
- External tags
- Direct map
- Separate "dirty" RAM not required
- 2-1-1-1 reads with two banks, 2-2-2-2 with one bank
- 32 KB to 1MB cache size
- One wait state writes on cache-hits
- Optional zero wait state writes
- Optional one wait state reads
o Other features:
- Programmable for 10- or 16-bit internal I/O addressing
- Programmable drive on the DRAM and ISA bus signals
- Programmable memory access to define "fast-bus", local bus, slot
bus, non-cacheable and write-protect areas
- Input pin defines access to local bus devices
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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