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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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*VLSI...
**VL82C311 SCAMP-DT ?
***Info:
The VL82C310, VL82C311 and VL82C311L are Single Chip AT, Mid-range
Performance (SCAMP) Controllers for 286- or 386SX-based PC/AT compat-
ible systems. (the VL82C311L is for 286-based systems only.)
The VL82C310/VL82C311/VL82C311 includes the dual 82C37 DMA
controllers, dual 82C59A programmable interrupt controllers, 82C54
programmable inter- val timer, 82284 clock and ready generator, 82288
bus controller and the logic for address/data bus control, memory
control, shut down, refresh generation and refresh/DMA arbitration.
The VL82C310/VL82C311/VL82C311 Controllers (from hear-in referred to
as SCAMP Controllers unless referring to a specific Controller, which
will be called out by the device number) are designed to perform in
286- or 386SX- based PC/AT-compatible systems running up to 25 MHz,
and replace the following devices on the motherboard:
o Two 82C37A DMA controllers
o Two 82C59A interrupt controllers
o 82C54 timer
o 74LS612 memory mapper
o 82284 clock generator and ready interface
o 82288 bus controller
The SCAMP Controller also includes the following:
o Memory/refresh controller
o Port B and NMI logic
o Bus steering logic
o Turbo Mode control logic
o Parity checking logic
o Parity generation logic
The SCAMP Controller supports LIM EMS 4.0, 287 AMD 387SX numeric
coprocessors.
The memory controller logic is capable of accessing up to 16 MB of
on-board DRAM. There can be up to four banks of 256K, 1M, or 4M
attached in the system. the SCAMP Controller can drive four banks
without external buffering. Built-in Page Mode operation and two-way
interleaving allow the PC designer to maximize system performance
using low-cost DRAMs. Support is also included for zero and one wait
state operation of system DRAM.
There are 36 Mapping Registers in the SCAMP Controller for full EMS
4.0 standard support. The system allows backfill down to 256K for EMS
support and provides 24 mapping registers covering this space. Twelve
of the 36 Page Registers cover the EMS space from C0000h to EFFFFh.
All registers are capable of translating over the complete range of
on-board DRAM. Users preferring an alternate, plug-in EMS solution
can disable the on-board EMS system as well as system board DRAM. as
required, down to zero.
Shadowing features are supported on 16K boundarys between C0000h and
DFFFFh, and on 32K boundaries between A0000h and BFFFFh and between
E0000h and FFFFFh. Simultaneous use of EMS, shadowed ROM and direct
system board access is possible in a non-overlapping fashion
throughout this memory space. Control over four access options is pro-
vided. These controls are overridden by EMS in the segments for which
it is enabled. The options are:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.
The SCAMP Controller handles system board refresh directly and
controls the timing of slot bus refresh. Refresh is performed in the
standard PC/AT Mode where on- and off-board refreshes are performed
synchronously. Refreshes are staggered to minimize power supply
loading and attenuate noise on the VDD and VSS pins. In the SCAMP
Controller, refresh can be programmed to sup- port CAS-before-RAS
refresh operation or standard RAS-only refresh operation. The SCAMP
Controller supports the PC/AT standard refresh period of 15.625 us as
well as 125 us.
The VL82C310 (only) has eight Mapping Registers to support 32 MB of
JEIDA IC Memory Card, also known as PC Card. four of these registers
are used as pointers to the CPU memory space between A0000h and FFFFFh
and the other four point to four pages in the IC Memory Card.
The 287 numeric coprocessor is supported when the SCAMP Controller is
strapped for 286 Mode. When configured for 386SX Mode, the 387SX is
supported. A software coprocessor reset does not leave a 387SX in the
same state as the reset of a 287 does. The SCAMP Controller can be
programmed to disable these software resets if problems arise.
The interrupt controller logic consists of two 82C509 megacells with
eight interrupt request lines each for a total of 16 interrupts. The
two megacells are cascaded internally and two of the interrupt request
inputs are connected to internal circuitry, allowing a total of 13
external interrupt requests. There is a special programmable logic
included in the SCAMP Controller which allows glitch-free inputs on
all the interrupt request pins.
The interval timer includes one 82C54 counter/timer megacell. the
counter/timer has three independent 16-bit counters and six
programmable counter modes.
The DMA controllers are 82C37 compatible. Each controls data transfers
between an I/O channel and on- or off-board memory. DMA can transfer
data over the full 16 MB range available. There are internal latches
provided for latching the middle address bits output by the 82C37
megacells on the data bus, and 74LS612 memory mappers are
integrated provided to generate the upper address bits.
The SCAMP Controller can be programmed for asynchronous or synchronous
operation of the AT bus.
The SCAMP Controller also performs all the data buffer control
functions required for a 286- or 386SX based PC/AT system. Under the
control of the CPU, the SCAMP Controller routes data to and from the
CPU's D bus, the internal XD bus, and the slots (SD bus). The parity
is checked for D bus DRAM read operations. The data is latched for
synchronization with the CPU. Parity OS generated for all data written
to the D bus.
***Configurations:...
***Features:...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?
***Info:
VLSI Technology, Inc.'s VL82C380 is a highly integrated 32-bit
single-chip PC/AT controller with on-chip cache controller designed
for use in 386DX-based ISA systems operating at up to 40 MHz. Its
cache controller is designed with a look-aside, write- back
architecture for increased write performance as well as read
performance. Full coherency is maintained during DMA/Master Mode
cycles.
The VL82C380 is a highly integration solution. A complete system can
be implemented using only the CPU, BIOS, DRAM, VL82C380, VL82C113A
Combination I/O and 3 SSI TTL's, plus optional TAG and Data SRAMs.
Tag SRAMs can be either 8- or 9-bit (7- or 8-bit tag plus a dirty
bit). Dirty and Valid bits are optional, each may be disabled in order
to increase cacheable DRAM range. The Dirty bit, when used, indicates
that the cache has been updated but not the corresponding locations in
DRAM. The Valid bit, when used, indicates that both the cache and
corresponding DRAM locations have been updated.
Only on-board DRAM is cached, this prevents coherency issues
associated with caching system memory in the USA bus. Full coherency
is maintained during DMA/Master mode cycles, so flushing and
invalidating operations are unnecessary. set-up/sizing mode
(programmable) provides direct access to the cache data SRAMs.
The Memory Controller logic is capable of accessing up to 64 MB. There
can be up to 4 banks of 256K, 1M, or 4M DRAMs used in the system. The
VL82C380 can drive two banks without external buffering. Built-in
page-mode operations and up to 2-way interleaving allow the PC
designer to maximize system performance using low-cost
DRAMs. Programmable DRAM timing is provided for RAS precharge, RAS to
CAS delay, and CAS pulse width.
***Configuration:...
***Features:...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
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**Not sure if they actually exist...
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