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*Contaq . . . . . [no datasheets, some info]...
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*Intel...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5595 Pentium PCI System I/O <12/24/97
***Notes:...
***Info:...
***Versions:...
***Features:
o Integrated PCI-to-ISA Bridge
− Translate s PCI Bus Cycles into ISA Bus Cycles.
− Translate s ISA Master or DMA Cycles into PCI Bus Cycles.
− Provide s a Dword Post Buffer for PCI to ISA Memory cycles.
− Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA
Master Performance.
− Fully Compliant to PCI 2.1.
o Supports both Desktop and Mobile Advanced Power Management Logic
− Meets ACPI 1.0 Requirements.
− Supports Both ACPI and Legacy PMU.
− Supports Suspend to RAM.
− Supports Suspend to Hard Disk.
− Optionally Tri−state ISA bus in low power state.
− Supports Battery Management and LB/LLB/AC Indicator.
− Supports CPU's SMM Mode Interface.
− Supports CPU Stop Clock.
− Supports Power Button of ACPI.
− Supports three system timers and SMI# watchdog timer.
− Supports Automatic Power Control.
− Supports Modem Ring−in, RTC Alarm Wake up.
− Supports Thermal Detection.
− Supports GPIOs, and GPOs for External Devices Control.
− Supports Programmable Chip Select.
− Supports PCI Bus Power Management Interface Spec. 1.0
− Supports Pentium II Sleep State.
o Enhanced DMA Functions
− 8-, 16- bit DMA Data Transfer.
− Two 8237A Compatible DMA Controllers with Seven Independent
Programmable Channels.
− Provide the Readability of the two 8237 Associated Registers.
− Support Distributed DMA.
− Support PC/PCI DMA.
− Per DMA channel programmable in legacy, DDMA or PC/PCI DMA mode
operation.
o Integrated Two 8259A Interrupt Controllers
− 14 Independently Programmable Channels for Level- or Edge-
triggered Interrupts.
− Provide the Readability of the two 8259A Associated Registers.
− Support Serial IRQ.
− Support the Reroutability for the PCI Interrupts.
o Three Programmable 16-bit Counters compatible with 8254
− System Timer Interrupt.
− Generate Refresh Request.
− Speaker Tone Output.
− Provide the Readability of the 8254 Associated Registers.
o Integrated Keyboard Controller
− Hardwired Logic Provides Instant Response.
− Supports PS/2 Mouse Interface.
− Supports Keyboard Password Security or Hot Key Power On
Function.
− Supports Hot Key "Sleep" Function.
− Programmable Enable and Disable for Keyboard Controller and
PS/2 Mouse.
o Integrated Real Time Clock(RTC) with 256B CMOS SRAM
− Supports ACPI Day of Month Alarm/Month Alarm.
− Supports various Power Up events, such as Button Up, Alarm Up,
Ring Up, GPIO5/PME0# Up, GPIO10/ PME1# Up, Password Security Up,
and Hotkey Up.
− Supports various Power Down Events, like Software Power-down,
Button Power-down, and ACPI S3 Power-down.
− Supports Power Supply ’98.
− Provides RTC year 2000 solution.
o Integrated Frequency Ratio Control Logic for Pentium II CPU
o Universal Serial Bus Host Controller
− Open HCI Host Controller with Root Hub.
− Two USB Ports.
− Supports Legacy Devices.
− Supports Over Current Detection.
o Integrated Hardware Monitor Logic
− Up to 5 Positive Voltage Monitoring Inputs.
− Two Fan Speed Monitoring Inputs.
− One Temperature Sensings.
− Supports thermister- or diode- temperature sensing for Pentium
II CPU.
− Threshold Comparison of all Monitored Values.
o Supports I2C Serial Bus/ SMBUS
o Supports 2MB Flash ROM Interface
o 208 pins PQFP Package
o 5V CMOS Technology
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C286-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?
***Info:
The TOPCAT 286/386SX chip set from VLSI Technology, Inc. is a very
high-integration chip set for use in the design of PC/AT-compatible
based systems. This chip set is intended for use in 80286 or 80386SX
microprocessor-based systems with clock speeds from 12 to 25 MHz.
The TOPCAT 286/386SX chip set provides design engineers with a very
flexible, high- performance, low-cost board design solution for IBM
PC/AT-compatible desktop, laptop, portable, and hand-held computers.
The TOPCAT 286/386SX two-device chip set has been designed with the
highest integration consistent with economic and reliable system
design. It provides a complete board design using only four non-memory
devices including the microprocessor.
VLSI's TOPCAT 286/386SX chip set was designed with seven goals.
o Lowest system board cost
o Smallest board area requirement
o Highest performance in both cached and non-cached systems
o Single board design for:
- 12 to 15 MHz operation
- Cache or non-cache
- 512K byte to 32M byte memory using 256K, 1M and 4M bit DRAM
- Laptop or desktop applications
o Full hardware LIM EMS 4.0 support for highest possible performance
o Built-in, in-circuit test modes for easy board level testing
o The VL82C320A interfaces to the VL82C335 "look-aside" Cache
Controller
With VLSI's TOPCAT 286/386SX chip set, you can be assured that your
high-performance system design needs are met.
The VL82C320/VL82C320A contains the System Control and the Data
Buffering functions in a 160-lead quad flatpack. The System Controller
is designed to perform in 80286- and 80386SX-based systems with clock
speeds of 25 MHZ and below, and peripheral bus speeds up to 12MHz. The
System Controller functions are highly programmable via a set of
internal configuration registers. Defaults on reset for the
configuration registers mimic the compatibility requirements of the
original IBM PC/AT as closely as possible. The power-up defaults
allow any possible configuration of the system to boot at the CPU's
rated speed.
The System Controller handles system board refresh directly and
controls the timing of slot bus refresh that is actually performed by
the VL82C331 ISA Bus Controller. Refresh may be performed in coupled
or decoupled mode. The former method is the standard PS/AT- compatible
mode where on- and off-board refreshes are independent. Both may be
programmed for independent, slower than normal rates. This allows the
use of low-power, slow refresh DRAMs. The VL82C320/VL82C320A controls
all timing in both modes. In all cases, refreshes are staggered to
minimize power supply loading and attendant noise on the VDD and
ground pins. In sleep mode, refresh switches to CAS before RAS refresh
for maximum power savings. the physical banks of DRAM can be
logically reordered through one of the indexed configuration
registers. this DRAM remap option is useful n order to map out bad
DRAM banks allowing continued use of a system until repairs are
convenient. It also allows DRAM bank combinations not in the supported
memory maps to be logically moved into a supported configuration with-
out physically moving memory components.
The 160-lead VL82C331 ISA Bus Controller provides the functions of
DMA, page address register, timer, interrupt control, port B logic,
slot bus refresh address generation, and real-time clock. To avoid
problems with sensitive slot bus add-in cards, the Bus Controller
features "Bus Quiet" mode operation. when no valid slot bus accesses
are occurring, none of the slot bus data, addresses, or control lines
are driven. Built-in "Sleep" mode features work together with System
Controller special features to provide a low-power system idle state
for extension of battery life in portable, laptop, and hand-held
systems. If an interrupt occurs due to an external source or
dedicated, internal programmable timer, the Vus Controller "wakes up"
and resumes normal operation. The DMA channels have been upgraded to
provide a superset of AT functionality by allowing DMA to the entire
23M byte memory range of the TOPCAT 286/386SX chip set. Additional
functionality is provided via DMA wait state, clock and MEMR timing
programmability.
***Configurations:...
***Features:...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?...
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C310 SCAMP-LT ?...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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