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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*SIS...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:...
***Configurations:...
***Features:
o Support Intel/AMD/Cyrix Pentium CPU and Other Compatible CPU
Host Bus at 60/66 MHz and 3.3V Bus Interface
− Support the Pipelined Address of Pentium compatible CPU
− Support the Linear Address Mode of Cyrix CPU
o Support the Pipelined Address Mode of Pentium CPU
o Fully Compliant to A.G.P. Revision 1.0 Specification
o Meet PC97 Requirements
o Supports PCI Revision 2.1 Specification
o Integrated Second Level (L2) Cache Controller
- Write Back Cache Mode
- Support L2 Cache Flushing for entire L2 cache or specific
4K page
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 32K bits Dirty SRAM
- Integrated 32K bits Invalid SRAM
- Support Pipelined Burst SRAM
- Support 256K/512K/1MBytes Cache Sizes
- Cache Hit Read/Write Cycle of 3-1-1-1
- Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
- Support Single Read Allocation for L2 Cache
- Support Concurrency of CPU to L2 cache and A.G.P. master to
DRAM accesses
o Integrated DRAM Controller
- Support 6 RAS Lines for FPM/EDO/SDRAM DIMMs/SIMMs
- Support 2Mbytes to 768Mbytes of main memory
- Support Cacheable DRAM Sizes up to 256 MBytes.
- Support 256K/512K/1M/2M/4M/8M/16Mx N FPM/EDO/SDRAM DRAM
- Support 64 Mb DRAM Technology
- Support Parity Checker or ECC Function
- Support 3.3V or 5V DRAM
- Supports Symmetrical and Asymmetrical DRAM
- Support Concurrent Write Back
- Support CAS before RAS Refresh, Self Refresh
- Support Relocation of System Management Memory
- Programmable CAS#, RAS#, RAMWE# and MA Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Support FPM DRAM 5/6-3-3-3(-3-3-3-3) Burst Read Cycles
- Support EDO DRAM 5/6-2-2-2(-2-2-2-2) Burst Read Cycles
- Support SDRAM 5/6/7-1-1-1(-2/3-1-1-1) Burst Read Cycles
- Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Two Programmable Non-cacheable Regions
- Option to Disable Local Memory in Non-cacheable Regions
- Shadow RAM in Increments of 16 Kbytes
- Pseudo Directory/Page Scheme for Mapping Graphical Texture
Access to Physical Memory Address
- Built-in 8 Way Associative/16 Entries GART cache to Minimize the
Number of Memory Bus Cycles Required for Accessing Graphical
Texture Memory
- Programmable Counters to Ensure Guaranteed Minimum Access Time
for A.G.P., CPU, and PCI accesses
o Provides High Performance PCI Arbiter.
- Support up to 5 PCI Masters
- Support Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Support Concurrency between CPU to Memory and PCI to PCI
- Support Concurrency between CPU to 33Mhz PCI Access and 33Mhz
PCI to A.G.P. Access
- Support Concurrency between CPU to 66Mhz PCI Access and A.G.P.
to 33Mhz PCI Access
- Programmable Timers Ensure Guaranteed Minimum Access Time for
PCI Bus Masters, and CPU
o Integrated Host-to-PCI Bridge
- Support Asynchronous and Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Zero Wait State Burst Cycles
- Support IDE Posted Write
- Support Pipelined Process in CPU-to-PCI Access
- Support Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Support Memory Remapping Function for PCI master accessing
Graphical Window
o Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
- Support Asynchronous and Synchronous A.G.P. Clock
- Support 1X, and 2X Mode for A.G.P. 66/133 MHz 3.3V device
- Support Graphic Window Size from 4Mbytes to 256Mbytes
- Different arbitration policy for A.G.P. devices and 66Mhz PCI
devices.
- Translates Sequential CPU-to-A.G.P. Memory Write Cycles into
A.G.P. Bus (PCI66) Burst Cycles
- Zero Wait State Burst Cycles
- Support Pipelined Process in CPU-to-A.G.P. Access
- Support Advance Snooping for A.G.P. Master initiate system
memory access with PCI Cycles
- Support 8 Way, 16 Entries Page Table Cache to enhance A.G.P.
Read/Write Performance
- Support Both 1-Level and 2-Level GART (Graphic Address Re-
Mapping Table)
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Programmable Counters to Ensure Guaranteed Minimum Access Time
for Low Priority Request, CPU to A.G.P./and A.G.P. Master
Transaction
- Support PCI-to-PCI bridge function for memory write from 33Mhz
PCI bus to A.G.P. bus
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
- CPU-to-PCI66 Posted Write Buffer(CTAFF) with 8 DW Deep
- PCI66-to-Memory Posted Write Buffer(ATHFF) with 8 QW Deep
- A.G.P. Request Queue With the Depth of 32
- A.G.P. High Priority Write Queue with 64 QW Deep
- A.G.P. Low Priority Write Queue with 64 QW Deep
- A.G.P. High Priority Read Return Queue with 64 QW Deep
- A.G.P. Low Priority Read Return Queue with 64 QW Deep
o Fast PCI IDE Master/Slave Controller
- Bus Master Programming Interface for ATA Windows 95 Compliant
Controller
- Plug and Play Compatible
- Support Scatter and Gather
- Support Dual Mode Operation - Native Mode and Compatibility
Mode
- Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
- Support Multiword DMA Mode 0, 1, 2
- Support Ultra DMA/33
- Two Separate IDE Bus
- Two 16 DW FIFO for PCI Burst Transfers.
o Support NAND Tree for Ball Connectivity Testing
o 553-Balls BGA Package
o 0.35μm 3.3V CMOS Technology
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C286-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?
***Info:
The TOPCAT 286/386SX chip set from VLSI Technology, Inc. is a very
high-integration chip set for use in the design of PC/AT-compatible
based systems. This chip set is intended for use in 80286 or 80386SX
microprocessor-based systems with clock speeds from 12 to 25 MHz.
The TOPCAT 286/386SX chip set provides design engineers with a very
flexible, high- performance, low-cost board design solution for IBM
PC/AT-compatible desktop, laptop, portable, and hand-held computers.
The TOPCAT 286/386SX two-device chip set has been designed with the
highest integration consistent with economic and reliable system
design. It provides a complete board design using only four non-memory
devices including the microprocessor.
VLSI's TOPCAT 286/386SX chip set was designed with seven goals.
o Lowest system board cost
o Smallest board area requirement
o Highest performance in both cached and non-cached systems
o Single board design for:
- 12 to 15 MHz operation
- Cache or non-cache
- 512K byte to 32M byte memory using 256K, 1M and 4M bit DRAM
- Laptop or desktop applications
o Full hardware LIM EMS 4.0 support for highest possible performance
o Built-in, in-circuit test modes for easy board level testing
o The VL82C320A interfaces to the VL82C335 "look-aside" Cache
Controller
With VLSI's TOPCAT 286/386SX chip set, you can be assured that your
high-performance system design needs are met.
The VL82C320/VL82C320A contains the System Control and the Data
Buffering functions in a 160-lead quad flatpack. The System Controller
is designed to perform in 80286- and 80386SX-based systems with clock
speeds of 25 MHZ and below, and peripheral bus speeds up to 12MHz. The
System Controller functions are highly programmable via a set of
internal configuration registers. Defaults on reset for the
configuration registers mimic the compatibility requirements of the
original IBM PC/AT as closely as possible. The power-up defaults
allow any possible configuration of the system to boot at the CPU's
rated speed.
The System Controller handles system board refresh directly and
controls the timing of slot bus refresh that is actually performed by
the VL82C331 ISA Bus Controller. Refresh may be performed in coupled
or decoupled mode. The former method is the standard PS/AT- compatible
mode where on- and off-board refreshes are independent. Both may be
programmed for independent, slower than normal rates. This allows the
use of low-power, slow refresh DRAMs. The VL82C320/VL82C320A controls
all timing in both modes. In all cases, refreshes are staggered to
minimize power supply loading and attendant noise on the VDD and
ground pins. In sleep mode, refresh switches to CAS before RAS refresh
for maximum power savings. the physical banks of DRAM can be
logically reordered through one of the indexed configuration
registers. this DRAM remap option is useful n order to map out bad
DRAM banks allowing continued use of a system until repairs are
convenient. It also allows DRAM bank combinations not in the supported
memory maps to be logically moved into a supported configuration with-
out physically moving memory components.
The 160-lead VL82C331 ISA Bus Controller provides the functions of
DMA, page address register, timer, interrupt control, port B logic,
slot bus refresh address generation, and real-time clock. To avoid
problems with sensitive slot bus add-in cards, the Bus Controller
features "Bus Quiet" mode operation. when no valid slot bus accesses
are occurring, none of the slot bus data, addresses, or control lines
are driven. Built-in "Sleep" mode features work together with System
Controller special features to provide a low-power system idle state
for extension of battery life in portable, laptop, and hand-held
systems. If an interrupt occurs due to an external source or
dedicated, internal programmable timer, the Vus Controller "wakes up"
and resumes normal operation. The DMA channels have been upgraded to
provide a superset of AT functionality by allowing DMA to the entire
23M byte memory range of the TOPCAT 286/386SX chip set. Additional
functionality is provided via DMA wait state, clock and MEMR timing
programmability.
***Configurations:...
***Features:...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?...
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C310 SCAMP-LT ?...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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