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**M1217/M1209    386SX/SLC Single Chip (40MHz)    [no datasheet]   c91
***Notes:...
**M1219          386DX/486 ISA Cache? Single Chip [no datasheet]     ?
**M1419          386DX/486 ISA Cache  Single Chip [no datasheet]   c91
**Ml429/31/35    486 VLB/PCI/ISA      [no datasheet, some info] cOct93...
**M1439/31/45    486 VLB/PCI/ISA      [no datasheet, some info] <May95...
**M1489/87       FinALi-486 PCI Chipset                         <Feb95...
**M????          Genie, Quad Pentium  [no datasheet, some info]    c95...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97
***Notes:...
***Info:...
***Versions:...
***Features:
o   Static Intel 386SX compatible Core 
    - Operating Power Supply  5.0V 
    - Operating frequency 25Mhz to 40Mhz 
o   Memory Controller
    - Supports EDO DRAM 
    - Supports on board memory size up to 16M bytes for 386SX or 64M 
      bytes upgrade system using 256K, 512K, 1M, 4M or 16M SIMMs 
    - Supports up to 4-bank DRAM interface 
    - Page interleave DRAM access for FP mode 
    - Programmable shadow RAM from A to B segment in 128K byte and C 
      to F segment in 32K byte unit 
    - Provides "RAS only" refresh or "CAS before RAS” refresh types 
    - Parity generation and checking 
o   Peripheral Interface 
    - Includes 2 cascaded 8237 DMA controllers 
    - Includes 1 74612 memory mapper 
    - Includes 2 cascaded 8259 interrupt controllers 
    - Includes 1 8254 programming counter 
o   ISA Interface
    - Executes cycles for requests from CPU, DMA and ISA bus master 
    - Assembles or de-assembles data for multiple bus cycle or 
      unmatched data width 
    - Generates refresh signals to ISA slots during DRAM refresh 
      cycles 
o   Built-in RTC 
    - Internal Real Time Clock that provides 128 byte CMOS RAM 
o   Programmable 2 channels chip select 
    - Provide chip select for memory  or I/O device without external 
      address decode random logic 
o   Built-In PS2/AT Keyboard Controller
    - Internal PS2/AT keyboard controller and mouse 
o   PMU interface 
    - Supports CPU SMM mode, SMI feature 
    - Supports APM control 
    - Provides External Suspend mode switch 
    - Provides four (4) system states for power saving (On, Doze, 
      Standby, Suspend) 
    - Supports RTC alarm wake up control 
o   Expandable GPI/O signals
    - Provides sixteen External power control input and output signals 
    - Provides sixteen independent pin for general purpose input and 
      output signals 
o   Watchdog timer 
    - When timer times out , a system reset or NMI or IRQ happens 
o   IDE interface
    - Provides a decoder for external IDE connection
o   Packaging 
    - 208-pin PQFP package

**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in the configurations section  and below have been sourced
from the second.

"Although the 82497 Cache Controller  is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache  Controller is part  of the  Pentium Processor  (510\60, 567\66)
Chip  Set, the  two parts  are functionally  identical except  for the
differences noted in this section." - p491

Aside  from some  minor  differences in  pin  configuration, the  main
difference is the direct support  for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.


This  chip was  used on  the Pentium  90MHz CPU  complexes of  Intel's
Xpress  platform.   Specifically  the BXCPUPENT90  (Single  90MHz,  16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.

***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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