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**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?
***Info:...
***Configurations:...
***Features:...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99
***Notes:...
***Info & Features:
M1561 Overview

128-bit Super-Socket7  North Bridge for AMD-K6-III  with integrated 3D
and Video Highest-performance game playing in a single integrated chip

The M1561 integrates the following functionalities in a Unified Memory
Architecture PC:

o   3-D Graphics
o   2-D Windows Acceleration
o   VGA Display Controller
o   SDRAM Memory Controller
o   PCI Bus Interface

M1561  supports the  66/100/1XX MHz  Socket 7  Front Side  Bus.  It is
System Memory  Management (SMM)  and Advanced Configuration  and Power
Interface Specification (ACPI) compliant.

M1561 uses  66/100/1XX MHz SDRAM with LVTLL  input/output signals. The
chip supports up to four memory DIMMs.

Power supplies are 2.5V  for the core and 3.3V for most  of the I/O. A
5V  reference is  needed for  the  5V tolerant  PCI inputs.  Reference
voltages for ArtX and ArtX+ are  also needed.The part is packaged in a
35x35mm 492 ball Thermally Enhanced Ball Grid Array (T 2 BGA) package.

North Bridge Features
o   128-bit Data Streaming architecture for highest performance 
    SMA/UMA
o   PC99 compliant
o   100/66MHz CPU Front Side Bus, 1XXMHz ready
o   Standard PC-100/66 SDRAM (up to 1 GB) PC-1XX ready
o   33 MHz PCI 2.2 compliant I/O bus
o   ACPI power management
o   Compatible with single-chip ALi M1535D and M1543 South Bridges

Performance 3D Graphics by ArtX

o   First integrated North Bridge with hardware-accelerated geometry 
    transformation & lighting (T&L)
o   Setup engine
o   Delivers fastest real game performance
o   Revolutionary new parallel rendering architecture for state-of-
    the-art pixel fill rates
o   Industry-leading 8X Virtual AGPTM graphics performance and 
    functionality
o   Hardware features:
    - Accelerated floating point Geometry and texture coordinate
      transformation, clipping, perspective projection
    - Accelerated specular, diffuse, and ambient lighting
    - 3D points, lines, triangles, polygons
    - Perspective-correct trilinear-filtered MIP-mapped texture 
      mapping
    - Alpha blending
    - Exponential pixel fog
    - Depth, stencil buffering
    - Anti-aliasing
    - Framebuffer clear and copy

2D/Multimedia Features
o   30fps DVD playback with hardware acceleration (motion 
    compensation)
o   128-bit BitBLT engine, 256 raster operations
o   Full color RGBA, color expansion, color keying
o   YUV planar 4:2:0, 4:2:2 video overlay, video scaling and filtering

Display Controller
o   Up to 1600x1200 non-interlaced screen resolution
o   Hardware features:
    - Analog CRT monitor output
    - 32-bit full-color
    - Fully compliant VGA adapter
    - Downloadable RAMDAC, hardware cursor
o   VBE 3.0 support

Memory interface
o   128-bit PC100/PC66 SDRAM, PC-1XX Ready
o   Up to 2.1 Gbytes/second bandwidth

Drivers
o   Optimized driver for DirectX 7 with Direct3D, OpenGL ICD, HWMC 
o   and GDI acceleration on Windows 98 and Windows 2000
o   Dynamic memory allocation for texture
o   Drivers available for Windows 98, Windows 2000 and Windows NT 4.0

Packaging
o   492-BGA, 35x35mm

***Configurations:...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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