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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
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*SIS...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:
The SiS5591/5592 SiS5595 glueless P5 A.G.P. chipset provides a high
performance/cost index Desktop/Mobile solution for the Intel Pentium
P54C/P55C, AMD K5/K6, and Cyrix M1/M2 A.G.P. system.
The SiS5591/SiS5592 A.G.P./PCI controller integrated the Host-to-PCI
bridge, the L2 cache controller, the DRAM controller, the Accelerated
Graphics Port interface, and the PCI IDE controller. The L2 cache
controller can support up to 1 M P.B. SRAM, and the DRAM controller
can support EDO/FP/SDRAM memory up to 768 MB with optional ECC or
parity check function. The A.G.P. 1.0 compliance interface supports
both 1X, and 2X speed mode with sideband address capability. The
built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA/33 functionality.
SiS5591 and SiS5592 have some pin-out switching to facilitate the
main-board layout. SiS5591 pin assignment is based on the ATX form
factor, and SiS5592 pin assignment is based on the NLX form
factor. Beside the pin-out switching, SiS5591 and SiS5592 is totally
the same on the internal logic circuit.
The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the
DDMA, and Serial IRQ capability, the ACPI/Legacy PMU, the Data
Acquisition Interface, the Universal Serial Bus host/hub interface,
and the ISA bus interface which contains the ISA bus controller, the
DMA controllers, the interrupt controllers, and the Timers. It also
integrates the Keyboard controller, and the Real Time Clock (RTC). The
built-in USB controller, which is fully compliant to OHCI (Open Host
Controller Interface), provides two USB ports capable of running
full/low speed USB devices. The Data Acquisition Interface offers the
ability of monitoring and reporting the environmental condition of the
PC. It could monitor 4 positive analogue voltage inputs, 2 Fan speed
inputs, and one temperature input.
***Configurations:...
***Features:...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97
***Info:
The Apollo-VP3 is a high performance, cost-effective and energy
efficient chip set for the implementation of AGP / PCI / ISA desktop
and notebook personal computer systems based on 64-bit Socket-7 (Intel
Pentium and Pentium MMX; AMD K5 / 5k86 and K6 / 6k86; and Cyrix / IBM
6x86 / M2) super-scalar processors.
The Apollo-VP3 chip set consists of the VT82C597 system controller
(472 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP). The
VT82C597 system controller provides superior performance between the
CPU, optional synchronous cache, DRAM, AGP bus, and PCI bus with
pipelined, burst, and concurrent operation. For pipelined burst
synchronous SRAMs, 3-1-1-1-1-1-1-1 timing can be achieved for both
read and write transactions at 66 MHz. Four cache lines (16
quadwords) of CPU/cache to DRAM write buffers with concurrent
write-back capability are included on chip to speed up cache read and
write miss cycles.
The VT82C597 supports six banks of DRAMs up to 1GB. The DRAM
controller supports standard Fast Page Mode (FPM) DRAM, EDO-DRAM,
Synchronous DRAM (SDRAM), and SDRAM-II with Double Data Rate (DDR) in
a flexible mix / match manner. The Synchronous DRAM interface allows
zero wait state bursting between the DRAM and the data buffers at
66Mhz. The six banks of DRAM can be composed of an arbitrary mixture
of 1M / 2M / 4M / 8M / 16MxN DRAMs. The DRAM controller also supports
optional ECC (single-bit error correction and multi-bit detection) or
EC (error checking) capability separately selectable on a bank-by-bank
basis.
The VT82C597 also supports full AGP v1.0 capability for maximum bus
utilization including 2x mode transfers, SBA (SideBand Addressing),
Flush/Fence commands, and pipelined grants. An eight level request
queue plus a four level post-write request queue with thirty-two and
sixteen quadwords of read and write data FIFO's respectively are
included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible
CPU/AGP/PCI remapping control is also provided for operation under
protected mode operating environments.
The VT82C597 supports two 32-bit 3.3 / 5V system buses (one AGP and
one PCI) with 64-bit to 32-bit data conversion. The 82C597 also
contains a built-in bus-to-bus bridge to allow simultaneous concurrent
operations on each bus. Five levels (doublewords) of post write
buffers are included to allow for concurrent CPU and PCI operation.
Consecutive CPU addresses are converted into burst PCI cycles with
byte merging capability for optimal CPU to PCI throughput. For PCI
master operation, forty-eight levels (doublewords) of post write
buffers and sixteen levels (doublewords) of prefetch buffers are
included for concurrent PCI bus and DRAM/cache accesses. The chipset
also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize
snoop overhead. In addition, the chipset supports advanced features
such as snoop ahead, snoop filtering, L1 write-back forward to PCI
master and L1 write-back merged with PCI post write buffers to
minimize PCI master read latency and DRAM utilization. The VT82C586B
PCI to ISA bridge supports four levels (doublewords) of line buffers,
type F DMA transfers and delay transaction to allow efficient PCI bus
utilization and (PC I-2.1 compliant). The VT82C586B also includes an
integrated keyboard controller with PS2 mouse support, integrated
DS12885 style real time clock with extended 256 byte CMOS RAM,
integrated master mode enhanced IDE controller with full scatter and
gather capability and extension to UltraDMA-33 / ATA-33 for 33MB/sec
transfer rate, integrated USB interface with root hub and two function
ports with built-in physical layer transceivers, Distributed DMA
support, and OnNow / ACPI compliant advanced configuration and power
management interface. A complete main board can be implemented with
only six TTLs.
The Apollo VP3 chipset is ideal for high performance, high quality,
high energy efficient and high integration desktop and notebook AGP /
PCI / ISA computer systems.
***Configurations:...
***Features:...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
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