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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
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*SIS...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:
The SiS5591/5592 SiS5595 glueless P5 A.G.P. chipset provides a high
performance/cost index Desktop/Mobile solution for the Intel Pentium
P54C/P55C, AMD K5/K6, and Cyrix M1/M2 A.G.P. system.
The SiS5591/SiS5592 A.G.P./PCI controller integrated the Host-to-PCI
bridge, the L2 cache controller, the DRAM controller, the Accelerated
Graphics Port interface, and the PCI IDE controller. The L2 cache
controller can support up to 1 M P.B. SRAM, and the DRAM controller
can support EDO/FP/SDRAM memory up to 768 MB with optional ECC or
parity check function. The A.G.P. 1.0 compliance interface supports
both 1X, and 2X speed mode with sideband address capability. The
built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA/33 functionality.
SiS5591 and SiS5592 have some pin-out switching to facilitate the
main-board layout. SiS5591 pin assignment is based on the ATX form
factor, and SiS5592 pin assignment is based on the NLX form
factor. Beside the pin-out switching, SiS5591 and SiS5592 is totally
the same on the internal logic circuit.
The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the
DDMA, and Serial IRQ capability, the ACPI/Legacy PMU, the Data
Acquisition Interface, the Universal Serial Bus host/hub interface,
and the ISA bus interface which contains the ISA bus controller, the
DMA controllers, the interrupt controllers, and the Timers. It also
integrates the Keyboard controller, and the Real Time Clock (RTC). The
built-in USB controller, which is fully compliant to OHCI (Open Host
Controller Interface), provides two USB ports capable of running
full/low speed USB devices. The Data Acquisition Interface offers the
ability of monitoring and reporting the environmental condition of the
PC. It could monitor 4 positive analogue voltage inputs, 2 Fan speed
inputs, and one temperature input.
***Configurations:...
***Features:...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97
***Info:...
***Configurations:...
***Features:
o PCI/ISA Green PC Ready
- Supports 3.3V or 5V interface to CPU, system memory, and / or
PCI bus
- Supports CPUs with internal voltages below 3.3V
- PC-97 compatible using VT82C586B South Bridge with ACPI Power
Management
o High Integration
- Single chip implementation for 64-bit Pentium-CPU, 64-bit system
memory, and 32-bit PCI interface
- VT82C590 Apollo VP2 Chipset: VT82C595 system controller and
VT82C586B PCI to ISA bridge
- Chipset includes UltraDMA-33 EIDE, USB, and Keyboard / PS2-Mouse
Interfaces plus RTC / CMOS on chip
- Six TTLs for a complete main board implementation
o Flexible CPU Interface
- Supports 64-bit Pentium, AMD 5k86 , AMD 6k86 and Cyrix 6x86 CPUs
- CPU external bus speed up to 66 Mhz (internal 200Mhz and above)
- Supports CPU internal write-back cache
- System management interrupt, memory remap and STPCLK mechanism
- Cyrix 6X86 linear burst support
- CPU NA# / Address pipeline capability
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support (with
global write enable feature)
- Flexible cache size: 0K/256K/512K/1M/2MB
- 32 byte line size to match the primary cache
- Integrated 10-bit tag comparator
- 3-1-1-1 read/write timing for PBSRAM access at 66 Mhz
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access at
66 Mhz
- Sustained 3 cycle write access for PBSRAM access or CPU to DRAM
and PCI bus post write buffers at 66 Mhz
- Data streaming for simultaneous primary and secondary cache
line fill
- System and video BIOS cacheable and write-protect
- Programmable cacheable region and cache timing
o Fast DRAM Controller
- Fast Page Mode/EDO/Synchronous-DRAM support in a mixed
combination
- Mixed 1M/2M/4M/8M/16MxN DRAMs
- 6 banks up to 512MB DRAMs
- Flexible row and column addresses
- 64-bit or 32-bit data width in arbitrary mixed combination
- 3.3v and 5v DRAM without external buffers
- Optional bank-by-bank ECC (single-bit error correction and
multi-bit error detection) for DRAM integrity
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
(14 MA lines)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Concurrent DRAM writeback
- Speculative DRAM access
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing
for EDO DRAMs at 50/60 MHz
- 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing
for EDO DRAMs at 66 MHz
- 6-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for
SDRAMs at 66 MHz
- 5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66 MHz
- 6-1-1-1-3-1-1-1 back-to-back access for SDRAM at 66 MHz
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate, CAS-before-RAS refresh and refresh
on populated banks only
o Intelligent PCI Bus Controller
- 32 bit 3.3/5v PCI interface
- Synchronous divide-by-two PCI bus interface
- PCI master snoop ahead and snoop filtering
- PCI master peer concurrency
- Synchronous bus to CPU clock with divide-by-two from the CPU
clock
- Automatic detection of data streaming burst cycles from CPU to
the PCI bus
- Five levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- Forty-eight levels (double-words) of post write buffers from PCI
masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for
access by PCI masters
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Complete steerable PCI interrupts
- Supports L1 write-back forward to PCI master read to minimize
PCI read latency
- Supports L1 write-back merged with PCI master post-write to
minimize DRAM utilization
- Provides transaction timer to fairly arbitrate between PCI
masters
- PCI-2.1 compliant
o Built-in nand-tree pin scan test capability
o 0.6um mixed voltage, high speed / low power CMOS process
o 328 pin Low-Profile BGA Package
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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