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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91
***Info:
The HT22  is an  advanced PC/AT compatible,  single-chip 80386SX/80286
system  design solution.   This highly  integrated single  chip allows
simple, low  cost system design  options while featuring  high perfor-
mance,  low  power  consumption,  and  minimum  board  space  require-
ments. Advanced  memory management  features include support  for page
mode,  2 or  4-way interleaving  in both  pipelined  and non-pipelined
modes.  The EMS  4.0 hardware implementation features dual  sets of 32
registers   with  full   context  support   for   highest  performance
optimization  of  extended local  memory  accesses.   An advanced  EMS
hardware  write-protect option  has  been added  for  maximum EMS  4.0
compatibility. The HTZ2 supports 256K, 1M  and 4MB DRAMs in 1 by 1 and
1 by 4 device configurations for up to 20MB of on-board system memory.
16MB  is  addressed  directly   by  system  resources,  the  remainder
addressed by the EMS mode.

A flexible Shadow  RAM option for System and Video BIOS  as well as 8-
16-bit BIOS options adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT22 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC  core logic requirements. The chip  also contains all
the  necessary  address buffers,  data  transceivers, memory  drivers,
parity  checking   and  supporting  circuitry  for   a  complete  high
performance computer  solution.  An  asynchronous AT Bus  clock allows
for  a constant 8MHz  Bus clock  rate for  highest bus  device compat-
ibility as  defined in IEEE  Spec P996. This  device is packaged  in a
208-pin Plastic Quad Flat Pack.

***Configurations:...
***Features:...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9351   80386DX Page Interleave Memory Controller (33MHz)         ?
***Info:
The SL9351 Memory Controller supports  PC/ AT systems based on Intel's
80386DX microprocessor. It  is a member of VIA's  FlexSet family which
utilizes the same  core logic across the entire  PC/ AT spectrum.  The
SL9351 is backward compatible with existing memory controllers for the
80386DX (SL9350).  Boards designed using  the SL9350 can be  used with
the new SL9351 without modifications  and with existing BIOS. In order
to  take advantage  of the  SL9351's many  new  programmable features,
minor board modification and a  modified BIOS is required for enhanced
performance.

The SL9351  offers the advanced memory control  functions and features
needed  to  develop high  performance  PC/  AT  systems without  using
external TTL  Logic. The SL9351 supports two-way  page interleave mode
for 80386DX based  designs. The Page interleave option  can be enabled
or disabled using the  configuration registers. All memory banks which
are interleaved use the same type of memory.  Designers can enable the
staggered RAS option during refresh, which minimizes power surge. Both
pipeline and non-pipeline modes are supported by enabling or disabling
the next address controls, and providing ready at the correct time.

***Versions:...
***Features:...
**SL9352   80386DX System and Memory Controller              <06/12/90...
**SLXXXX   Other chips...
**
**VT82C470     "Jupiter", Chip Set (w/o cache) 386 [no datasheet]    ?
**VT82C475     "Jupiter", Chip Set (w/cache) 386   [no datasheet]    ?
**VT82C486/2/3 "GMC chipset"            [no datasheet, some info]    ?...
**VT82C495/480 "Venus" Chip Set                    [no datasheet]    ?
**VT82C495/491 ? EISA Chip Set          [no datasheet, some info]  <93...
**VT82C496G    Pluto, Green PC 80486 PCI/VL/ISA System       <05/30/94...
**VT82C530MV   3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M    Apollo Master, Green Pentium/P54C             <06/22/95...
**VT82C580VP   Apollo VP,  Pentium/M1/K5 PCI/ISA System      <02/15/96...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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