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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**5595       Pentium PCI System I/O                          <12/24/97
***Notes:...
***Info:
SiS5595  is a  highly integrated  system I/O  that constitutes  a high
performance, rich featured, yet glueless solution for both Pentium and
Pentium  II  systems.   

The SiS5595 PCI  system I/O integrates the PCI-to-ISA  bridge with the
DDMA and PC/PCI  DMA, Serial IRQ capability, the  ACPI/Legacy PMU, the
Data  Acquisition   Interface,  the  Universal   Serial  Bus  host/hub
interface,  and the  ISA bus  interface,  which contains  the ISA  bus
controller, the  DMA controllers,  the interrupt controllers,  and the
Timers.  It also integrates the Keyboard controller, and the Real Time
Clock (RTC).  The built-in USB controller, which is fully compliant to
OHCI (Open Host Controller  Interface), provides two USB ports capable
of running full/low speed  USB devices. The Data Acquisition Interface
offers  the  ability of  monitoring  and  reporting the  environmental
condition  of the  PC.  It  could monitor  5  positive analog  voltage
inputs, 2  Fan speed inputs,  and one external temperature  inputs. It
also integrates the automatic power control logic to control the power
ON/OFF for ATX power supply.  In addition, SiS5595 also integrates the
thermal  detection and frequency  ratio control  logic for  Pentium II
CPU.

***Versions:...
***Features:...
**950        LPC I/O                                         <07/16/99...
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*UMC...
**UM82152      Cache Controller (AUStek A38152 clone)              <91
***Info:
The  UM82152 is a  high-performance cache  controller for  Intel 80386
based   systems  and   provides   high  levels   of  integration   and
functionality.  It interfaces  directly  to the  80386; no  additional
support  logic  is required.   A  complete  32-kilobyte  cache can  be
designed with just one UM82152 and four 8K by 8-bit static RAMs.

The  UM82152 architecture  enables easy  design-in with  current speed
versions  of  the  80386,  and  simple  migration  to  faster  version
processors with no alteration to system or memory design.

The 80386,  operating in  pipelined mode with  the UM82152,  runs with
zero  wait states during  a cache  hit (requested  data is  present in
cache). If  the data is not  present (cache miss), it  is fetched from
main  memory by  the  UM82152.  This  approach  yields the  high-speed
performance  of fast  SRAMs for  code and  data most  frequently used,
while  providing design  economies (such  as board  space  savings and
lower component costs)  by storing infrequently used code  and data in
slower  dynamic RAM (with  cycle times  greater than  125 nanoseconds)
that  can  be  located  in  large  memory  banks  either  on-board  or
off-board.

The reduced system bus  traffic inherent in the UM82152 implementation
produces system performance gains by  freeing the bus for use by other
devices.

***Versions:...
***Features:...
**UM82C852     Multi I/O For XT                                    <91...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
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