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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**5595 Pentium PCI System I/O <12/24/97
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**UM82152 Cache Controller (AUStek A38152 clone) <91
***Info:
The UM82152 is a high-performance cache controller for Intel 80386
based systems and provides high levels of integration and
functionality. It interfaces directly to the 80386; no additional
support logic is required. A complete 32-kilobyte cache can be
designed with just one UM82152 and four 8K by 8-bit static RAMs.
The UM82152 architecture enables easy design-in with current speed
versions of the 80386, and simple migration to faster version
processors with no alteration to system or memory design.
The 80386, operating in pipelined mode with the UM82152, runs with
zero wait states during a cache hit (requested data is present in
cache). If the data is not present (cache miss), it is fetched from
main memory by the UM82152. This approach yields the high-speed
performance of fast SRAMs for code and data most frequently used,
while providing design economies (such as board space savings and
lower component costs) by storing infrequently used code and data in
slower dynamic RAM (with cycle times greater than 125 nanoseconds)
that can be located in large memory banks either on-board or
off-board.
The reduced system bus traffic inherent in the UM82152 implementation
produces system performance gains by freeing the bus for use by other
devices.
***Versions:...
***Features:...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
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