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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97
***Info:
Nowadays, several PC form factors exist in the PC board market, such
as NLX, LPX, ATX and Baby-AT form factors. Due to the different
placements of the form factor, PC chipsets should be prepared for
different board layouts. As a result, SiS chips based on compatible
logic design provide two series of chipsets, SiS 5597 and SiS 5598, to
assist board designers for their board layouts.
SiS 5597’s pin assignment is based on NLX, and LPX form factor, while
SiS 5598’s is defined on the basis of ATX and Baby-AT form factors. In
the next few chapters, you will read “SiS Chip” which indicates either
SiS 5597 or 5598 chipsets, decided by the placements of form factors
on PC boards of customers.
The SiS Chip with built-in VGA controller is a highly integrated
single chip solution for Pentium PCI/ISA system. A portion of on-board
DRAM is shared with the integrated VGA controller. In that way, the
system cost is substantially reduced and on-board DRAM can be used
flexibly.
The SiS Chip consists of Host-to-PCI bridge function, PCI to ISA
bridge function, PCI IDE function, Universal Serial Bus host/hub
function, Integrated RTC, Integrated Keyboard Controller and Graphics/
Video accelerate function.
SiS Chip supports Enhanced Power Management, including legacy Power
Management Unit and Advanced Configuration and Power Interface
(ACPI). It also supports ATA Synchronous DMA transfer protocol to
improve the IDE performance and Common Architecture for moving ISA
function to PCI to improve system performance.
***Configurations:...
***Features:...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C230 286AT MORTAR Chip Set <91
***Info:
The UMC's MORTAR (286AT) Chip Set UM82C230 series provides an economic
alternative for building a reliable IBM PC/AT compatible system. A
commercial 12MHZ/0 wait state, 4MByte main memory system and
math-coprocessor can be easily built by using 3 VLSIs, 8 logic
components plus memory and processor.
The UM82C230 MORTAR chipset consists of the UM82C231 System/Memory
Controller, the UM82C232 Data/Address Buffer and the UM82C206
Integrated Peripherals Controller (IPC).
As shown in the System Block Diagram, [see datasheet] there are three
data buses: local data bus, AT data bus and peripheral data (XD) bus.
The local DRAM, EPROM and Numerical Processor are located on the local
data bus. The UM82C206 and 8042 Keyboard Controller sit on the XD bus.
The AT data bus was driven by the UM82C232 directly which conveys the
data to/from the AT Channel Adaptors.
The address bus architecture is also very simple; local CPU address
bus, local DRAM address bus (MA), peripheral address bus (XA) and AT
address bus. The local address bus is shared between CPU, UM82C231 and
UM82C206. The MA bus is used by the local DRAM only. Most of the
system board devices are attached to the XA bus, like UM82C232,
UM82C206, ROMs and 8042. Some AT address lines are driven by the
UM82C231 or UM82C232 directly; the others are buffered.
The UM82C231 provides synchronization and control signals for all
buses. The UM82C231 also distinguishes if the current cycle is local
memory cycle. Upon detecting that it is a local DRAM cycle, no AT
control signals are sent out to the AT channel. The UM82C231 is based
on the memory configurations to complete the current cycle with
fastest response. If the cycle is AT cycle, the UM82C231 sends out the
control signals sequentially which are then used by the adaptors or
system board devices to receive the write data or to send the fetched
data. Then, depending on the status signals sent back by the adaptors
or system board devices, the UM82C231 determines which kind of AT
cycles to perform: 8-bit, 16-bit, bus conversion, wait state insert,
or wait state cycle.
The UM82C232 Data/Address buffer provides the buffering and latching
between the CPU local data bus, AT bus and XD bus. The parity bit
generation and parity bit checking logic resides in the UM82C232 also.
During DMA cycles, the UM82C232 latches the address from XD, which is
sent by the UM82C206, and transfers to XA bus.
***Configurations:...
***Features:...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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