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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89
***Info:
The Texas Instruments TACT83000 AT Chip Set is designed for cached and
noncached 386-based  PC-AT compatible systems running at  speeds up to
33 MHz.  Manufactured with high-speed  1-um CMOS EPIC  technology, the
chip set is functionally partitioned into three devices: the TACT83443
AT Bus Interface Unit (ATU),  the TACT83442 Memory Control Unit (MCU),
and the  TACT83441 Data  Path Unit  (DPU).  The ATU  is packaged  in a
208-lead  plastic quad  flatpack  (QFP),  while the  MCU  and DPU  are
packaged in 100-lead plastic QFPs

These three chips, along with four other logic chips, comprise all the
logic  necessary for  a  fully compatible  16-bit 3868X-based  system.
Since one DPU provides a 16-bit data path, a 32-bit 386DX-based system
requires an additional DPU.

With software-controlled configuration registers  on board the ATU and
MCU,  the  chip set  supports  a wide  variety  of  PC system  config-
urations.  For complete programming  details, see the TACT8300 AT Chip
Set User’s Guide, literature number SRZU001.

***Configurations:...
***Features:
o   High-Speed 1-um CMOS Technology Supports System Speeds up to 
    33 MHz
o   Fully AT-Compatible 386 Three-Chip SX, Four-Chip DX Solutions
o   Only Four Additional Logic Chips Needed
o   Major Features Programmable Through Software
o   TACT83442 Memory Control Unit (MCU)
    - Cascadable up to Eight Devices
    - Address Range of up to 32M Byte Per Device, 256M Byte Fully 
      Cascaded
    - Supports 256K-, 1M-, and 4M-Bit DRAMs in Normal, Page, Word-
      interleave, and Page Block-interleave Modes
    - Programmable DRAM Timing Parameters
    - Supports up to Two Memory Banks for 32-Bit Systems and Four 
      Banks for 16-Bit Systems
    - Can Directly Drive up to 36 DRAM Devices
    - Shadow RAM Available Between 0C 0000h and 0F FFFFh
    - Contains Global Page Mapping RAM Allowing Remap of 
      - 64K-Byte Memory Blocks Above 1M Byte
      - 16K-Byte Memory Blocks Below 1M Byte
o   TACT83443 AT Bus Interface Unit (ATU)
    - Internal Clock Switching Between Two Independent Frequencies 
      Controlled by Software
    - Asynchronous AT Bus Interface With Write Buffer Option
    - Full AT Direct-Drive Capability
    - Extended Direct Memory Access Mode for 32-Bit Operation
    - Fast CPU Reset and A20 GATE Modification
    - Numeric Processor Interface for 387SX, 387DX, and Weitek 3167
    - Integrates All Essential AT Peripherals
    - Real Time Clock With 128-Byte CMOS RAM
o   TACT83441 Data Path Unit (DPU)
    - 8- and 16-Bit Data Bus Sizing
    - Data Path Cascadable to 32 Bits
    - Write Buffer Capability for AT Bus Access
    - Supports Posted Write Operations From Cache Controller
    - Parity Generation and Checking Logic

**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...