[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:
The SiS5591/5592 SiS5595 glueless P5 A.G.P. chipset provides a high
performance/cost index Desktop/Mobile solution for the Intel Pentium
P54C/P55C, AMD K5/K6, and Cyrix M1/M2 A.G.P. system.
The SiS5591/SiS5592 A.G.P./PCI controller integrated the Host-to-PCI
bridge, the L2 cache controller, the DRAM controller, the Accelerated
Graphics Port interface, and the PCI IDE controller. The L2 cache
controller can support up to 1 M P.B. SRAM, and the DRAM controller
can support EDO/FP/SDRAM memory up to 768 MB with optional ECC or
parity check function. The A.G.P. 1.0 compliance interface supports
both 1X, and 2X speed mode with sideband address capability. The
built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA/33 functionality.
SiS5591 and SiS5592 have some pin-out switching to facilitate the
main-board layout. SiS5591 pin assignment is based on the ATX form
factor, and SiS5592 pin assignment is based on the NLX form
factor. Beside the pin-out switching, SiS5591 and SiS5592 is totally
the same on the internal logic circuit.
The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the
DDMA, and Serial IRQ capability, the ACPI/Legacy PMU, the Data
Acquisition Interface, the Universal Serial Bus host/hub interface,
and the ISA bus interface which contains the ISA bus controller, the
DMA controllers, the interrupt controllers, and the Timers. It also
integrates the Keyboard controller, and the Real Time Clock (RTC). The
built-in USB controller, which is fully compliant to OHCI (Open Host
Controller Interface), provides two USB ports capable of running
full/low speed USB devices. The Data Acquisition Interface offers the
ability of monitoring and reporting the environmental condition of the
PC. It could monitor 4 positive analogue voltage inputs, 2 Fan speed
inputs, and one temperature input.
***Configurations:...
***Features:...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99
***Info:...
***Versions:...
***Features:
o Low Pin Count Interface
- Comply with Intel LPC Interface Specification Rev. 1.0
(Sept. 29, 1997)
- Supports Serial IRQ Protocol
- Supports PCI PME# Interface
o PC98/PC99, ACPI Compliant
- PC98 & PC99 compliant
- Register sets compatible with "Plug and Play ISA Specification
Rev. 1.0a"
- ACPI V. 1.0 compliant
- Supports 9 logical devices
o Enhanced Hardware Monitor
- Built-in 8-bit Analog to Digital Converter
- 3 thermal inputs from remote thermistors or thermal diode or
diode-connected transistor
- 8 voltage monitor inputs (VBAT is measured internally.)
- WatchDog comparison of all monitored values
o Fan Speed Controller
- Provides Fan ON/OFF and PWM control
- 3 programmable Pulse Width Modulation (PWM) Fan control outputs
- Each PWM output supports 128 steps of PWM modes
- Monitors 3 Fan tachometer inputs
o Game Port
- Built-in 558 quad timers and buffer chips
- Supports direct connection of two joysticks
- Game port signals are multiplexed with GPIOs
o Two 16C550 UARTs
- Supports two standard Serial ports
- UART1 is dedicated for Serial port
- UART2 supports either Serial Port or IrDA 1.0/ASKIR
o Consumer Remote Control (TV remote) IR with Power-up Feature
o IEEE 1284 Parallel Port
- Standard mode -- Bi-directional SPP compliant
- Enhanced mode -- EPP V. 1.7 and 1.9 compliant
- High speed mode -- ECP, IEEE 1284 compliant
- Backdrive current reduction
- Printer power-on damage reduction
− Supports POST (Power-On Self Test) Data Port
o Floppy Disk Controller
- Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy
disk drives
- Enhanced digital data separator
- 3-Mode drives supported
- Supports automatic write protection via software
o 48 General Purpose I/O Pins
- Input mode supports switch de-bounce
- SMI is routed through GPIOs
o Flash ROM Interface
- Up to 4M bits flash supported
o Single 24/48 MHz Clock Inputs
o Single +5V Power Supply
o 128-Pin PQFP
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved