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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C281/282 Cache Sx/AT (386SX) <08/22/91
***Notes:...
***Info:...
***Configurations:...
***Features:
o Flexible DRAM Banks Configuration
- The 82C281/2 supports 256K, 1M, and 4M memory devices, total
main memory size can be up to 16MB. A total of 12 different
memory configurations are supported.
o Page Mode Operation
- Based on the memory configuration shown above [see datasheet],
the memory control unit inside the 820281/2 performs page mode
of operation with a varying block size of 1k, 2k, or 4k bytes
for 256k, 1M, or 4M DRAMs respectively.
o System BIOS Shadow RAM
- The 820281/2 memory control unit provides shadow RAM feature for
several areas of memory system BIOS, video BIOS, and adapter
BIOS.
o Memory Remapping
- If shadow RAM feature is not utilized for the memory area
between 0D0000H - 0EFFFFH, then memory remapping is possible.
The local DRAM areas, 0A0000H - 0BFFFFH and 0D0000H - 0EFFFFH, a
total of 256 KByte, are remapped to the top of total system
memory. The areas for 0F0000H-0FFFFFH (system BIOS) and
0C000H-0CFFFFH (Video BIOS) are reserved for shadow RAM purpose.
o Flexible Multiplexed DRAM Address
o Cache Control Subsystem
- Direct-mapped posted write cache control function provides a low
cost alternative to enhance the system performance by up to 50%.
In order to simplify the design without increasing the system
cost or decreasing performance, the 82C281/2 has been designed
to support only non-pipeline mode for systems with cache memory.
The 82C281/2 offers the following cache control features:
- Flexible Cache Memory Size
- 4MB Cacheabie main memory by using 16KB low cost SRAM.
- 8MB Cacheable main memory by using 32KB low cost SRAM.
- Cache 16MB main memory by using 64KB low cost SRAM.
- Increase the cache size beyond 64KB up to 512KB
- Cache Line Size 4 Byte
- Burst mode memory prefetch is supported by the 82C281/2.
During cache read miss cycles, the memory control subsystem
will perform two consecutive read cycles to fetch 4 bytes
from main memory before terminating the cycle by sending
RDYO# signal to 3868X.
- Non-Cacheable Area
The non-cacheable areas are predefined as indicated below:
- I/O address space
- memory address between 0A0000H and 0FFFFFH.
- any memory address beyond the current configured memory
size.
- programmable non-cacheable memory area as defined by
82C281/2 internal registers.
- 82C281 Posted Write Cache
- The 820281 supports flexible direct-mapped cache with posted
write through update of main memory. By programming the
internal register, the post write control signals are
provided by the 820281 to support a one level write buffer.
With posted write, the CPU write cycles can be completed in
2 CPU T-States, thereby increasing system performance.
- 820282 Write Through Cache
- The 820282 supports a write-through cache system which
allows the designer to reduce system cost by eliminating two
F244's and two F373‘s with only a slight reduction in system
performance (5-10%).
- AT Bus Control
- The 820281/2 AT bus control unit handles all of the AT bus
operations and the DMA/Refresh arbitration. The AT bus
control unit supports the following features:
- Programmable AT Bus Clock - The AT bus clock, ATCLK. can
be programmed as CLK2/6, which is default, or CLK2/4.
- Turbo Switch - The 820281/2 provides a turbo switch
feature that allows users to change the system clock
speed. A programmable bit will enable or disable this
turbo function. When the turbo function is enabled by
setting reg[14H], bit[1] to 1, the 82C281/2 turbo pin
then determines the system clock speed. A low on the
turbo pin forces the CPU to run at the current AT bus
speed which IS CLK2/6 or CLK2/4.
**82C283 386SX System Controller c:91...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:
The P5 A.G.P./VGA chipset, SiS530/5595, provides a high performance/
cost index Desktop/Mobile solution for the Intel Pentium P54C/P55C,
AMD K5/K6/K6-II, Cyrix M1/M2 and other compatible Pentium CPU with 3D
A.G.P. VGA system.
The Host, PCI, 3D A.G.P. Video/Graphics & Memory Controller, SiS530
integrates the Host- to-PCI bridge, the PCI interface, the L2 cache
controller, the DRAM controller, the high performance hardware 2D/3D
VGA controller, and the PCI IDE controller.
The Host interface supports Synchronous/Asynchronous Host/DRAM
clocking configuration to eminently improve the system performance and
DRAM compatibility issues.
The L2 cache controller can support up to 2 MB P.B. SRAM, and the DRAM
controller can support SDRAM memory up to 1.5 GBytes with three
double-sided SDRAM DIMMs configuration. The cacheable DRAM sizes
support up to 256 MBytes.
The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA33/66 function that support the data transfer rate up to 66
MB/s. It provides the separate data path for two IDE channels that can
eminently improve the performance under the multi-tasking environment.
The A.G.P. internal interface is supported for integrated H/W 3D VGA
controller. The integrated VGA controller is a high performance and
targeted at 3D graphics application. In addition, the integrated 3D
Video/Graphics controller adopts the 64bits 100MHz host bus interface
high technology to improve the performance eminently. To cost-
effective the PC system, the share system memory architecture will be
adopted and it can flexibly using the 2MB, 4MB and 8MB frame buffer
size from programming the system BIOS. [something got confused in
translation there didn't it?] To enhance the system performance,
SiS530 also supports the local frame buffer solution and memory sizes
can support up to 8MB with SDRAM and SGRAM.
In addition to provide the standard interface for CRT monitors, it
also provides the Digital Flat Panel Port (DFP) for a standard
interface between a personal computer and a digital flat panel
monitor. This port allows a host computer to connect directly to an
external flat panel monitor without the need for analog-to-digital
conversion found in most flat panel monitors today. As for DVD
solution, the integrated 3D VGA controller also support DVD H/W
accelerator to improve the DVD playback performance.
The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the
DDMA, PC/PCI DMA and Serial IRQ capability, the ACPI/Legacy PMU, the
Data Acquisition Interface, the Universal Serial Bus host/hub
interface, and the ISA bus interface which contains the ISA bus
controller, the DMA controllers, the interrupt controllers, the Timers
and the Real Time Clock (RTC). It also integrates the Keyboard
Controller and PS/2 mouse interface that can support keyboard power on
function for users to power on system by entering the hot key or
password from keyboard. The built-in USB controller, which is fully
compliant to OHCI (Open Host Controller Interface), provides two USB
ports capable of running full/low speed USB devices. The Data
Acquisition Interface offers the ability of monitoring and reporting
the environmental condition of the PC. It could monitor 5 positive
analog voltage inputs, 2 Fan speed inputs, and one temperature input.
In addition, SiS5595 also supports ACPI function to meet Advanced
Configuration and Power Interface (ACPI) 1.0 specification for Windows
98 environment, it can support power-management timer, Power button,
Real-time clock alarm wake up, more sleeping state, ACPI LED for
sleeping and working state, LAN wake up, Modem Ring In wake up, and
OnNow initiative function.
***Configurations:...
***Features:...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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