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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*Motorola...
*OPTi...
**82C822 PCIB (VLB-to-PCI bridge) c:94
***Notes:...
***Info:
OPTi's 82C822 VESA local bus to PCI Bridge (PCIB) chip is a high
integration 208-pin PQFP device designed to work with VESA VL bus
compatible core logic chipsets. The 82C822 PCIB provides interface to
the high performance PCI bus and is fully compliant to the PCI Version
2.0 specification. The 82C822 requires no glue logic to implement the
PCI bus interface and hence it allows designers to have a highly
integrated motherboard with both VESA local bus and PCI local bus
support. The PCIB chip offers premium performance and flexibility for
VESA VL-based desktop systems running up to 50MHz. The 82C822 PCIB can
be used with OPTi's 82C802G core logic and 82C602 buffer chipsets to
build a low cost and power efficient 486-based desktop solution. It
also works with OPTi 82C546/547 chipset to build a high performance
PCI/VL solution based on the Intel P54C processor.
The 82C822 PCIB provides all of the control, address and data paths to
access the PCI bus from the VESA Local bus (VL bus). The 82C822
provides a complete solution including data buffering, latching,
steering, arbitration, DMA and master functions between the 32-bit VL
bus and the 32-bit PCI bus.
The PCIB works seamlessly with the motherboard chipset bus arbiter to
handle all requests of the host CPU and PCI bus masters, DMA masters,
I/O relocation and refresh. Extensive register and timer support are
designed into the 82C822 to implement the PCI specification.
The 82C822 is a true VESA to PCI bridge. It has the highest priority
on CPU accesses after cache and system memory. It generates LDEV#
automatically and then compares the addresses with its internal
registers to determine whether the current cycle is a PCI cycle. When
a cycle is identified as PCI cycle, the 82C822 will take over the
cycle and then return RDY# to the CPU. If not, the 82C822 will give up
the cycle to the local device or, in the case of an ISA slave,
generate a BOFF# cycle to the CPU. This action will abort the cycle
and allow the CPU to rerun the cycle.
The 82C822 includes registers to determine shadow memory space, hole
locations and sizes to allow the 82C822 to determine which memory
space should be local and which is located on the ISA bus. Upon access
to memory, the 82C822 can determine whether or not the cycle is a PCI
access by comparing the cycle with its internal registers.
***Versions:...
***Features:...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95
***Info:
The SiS 486-VIP (VESA/ISA/PCI) chips are two-chip solution ideally for
Intel's 80486, SL Enhanced 486, P24D/P24T/DX4 CPU, AMD's 486, Enhanced
Am486 and Cyrix's Cx486 (M7)/Cx 5x86 CPU based on green AT system. By
supporting the most popular industrial standard system interfaces, it
provides flexible configurations for system design and applications.
The SiS85C496 PCI & CPU Memory Controller (PCM) integrates the Host
Bridge (Host Interface), the cache and main memory DRAM Controller,
the PCI Bridge, the built-in IDE Controller, and the FS-Link Bus (Fast
Slow Link Bus). It provides the address paths and bus control for
transfers among the Host (CPU/L1 cache), main memory (L2 cache and
DRAM), the Peripheral Component Interconnect (PCI) Bus, and the
FS-Link Bus. The L2 cache controller supports both write-through and
write-back cache policies and cache sizes up to 1 MBytes. The cache
memory can be built using standard asynchronous SRAMs. The main
memory DRAM controller interfaces DRAM to the Host Bus, PCI Bus, and
FS-Link Bus. Up to eight single sided SIMMs or four double sided SIMMs
provide a maximum of 255 MBytes of main memory. The installation of
DRAM SIMMs is "Table-Free", which allows the SIMMs be installed into
any slot location and any combinations. The built-in IDE hard disk
controller allows CPU accessing hard disk and also provides higher
system integration with lower system cost. The 85C496 is intended to
be used with the SiS85C497 which is a AT Bus Controller with built-in
206 controller.
The SiS85C497 AT Bus Controller and Megacells (ATM) provides the
interface between PCI/CPU/Memory Bus (fast machine) and the ISA Bus
(slow machine). It also integrates many of the common I/O functions
in today's ISA based PC systems. The 85C497 comprises the FS-Link
interface (Fast-Slow Link interface), ISA bus controller , DMA
controller and data buffers to isolate the FS-Link Bus from the ISA
Bus and to enhance performance. It also integrates a 14 channel
edge/level interrupt controller, refresh controller, a 8-bit BIOS
timer, three programmable timer/counters, non-maskable-interrupt (NMI)
control logic, Power Management Unit, and RTC. Figure 1 .1 [see
datasheet] shows the system block diagram.
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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