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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*OPTi...
**82C281/282 Cache Sx/AT (386SX) <08/22/91
***Notes:...
***Info:
The 82C281/2 is a highly integrated AT system logic VLSI for high end
386 Sx AT systems. It integrates the logic for local DRAM control, AT
bus control, cache memory control, and data bus control and is
designed for systems running at 16MHz, 20MHz, and 25MHz.
A high performance, compact 386 Sx/AT system can be implemented easily
with 82C281/2 and standard peripheral controllers like the 82C206 or
the VLSI 82C100 plus Dallas Semiconductor DS1287.
2 System Operation
The following sections describe the detailed system operations of the
82C281 /2 based Sx-AT design.
2.1 Reset
The power good (PWRGD) signal from power supply drives the system into
the initial state when it is asserted low. The 82C281/2 forces CPURST,
SYSRST, and NPRST high as soon as PWRGD becomes inactive. When the
PWRGD is high, the chip deactivates the CPURST, SYSRST, and NPRST
after 128 CLK2 cycles.
2.2 Cache Interface
The 82028112 cache control unit monitors the HIT# pin and the internal
NCA# signals to determine if it is a cache hit or cache miss
cycle. During the cache read miss cycle, the cache controller asserts
TAGWE# to update the TAG RAM, CAWE# is also asserted to update the
cache data memory.
The A1 CNT output will be forced high then low to toggle CPU address
bit 1 to cache data memory to achieve the prefetch.
During cache write hit cycles, the cache controller asserts the CAWE#
signal to update the cache data memory.
2.3 Local DRAM Interfaces
Local DRAM is located on the CPU local data bus and is buffered by a
F244 and F373 buffer. During CPU read cycles data is routed from main
memory to CPU through F244’s Which are controled by LMRD#. During CPU
write cycles, data is latched by F373 latches with the PDLTH signal
from the 82C281/2 while DWE# controls the transceivers' enable. The
main memory subsystem asserts the LMRD# while CPU, DMA, and external
master card reads the local DRAM. DWE# is asserted during local DRAM
memory write.
For local memory read cycles, the memory controller reads two bytes at
a time. The read data passes into 82C281/2 where the parity checking
function is executed.
For the local memory write cycles, the data bus control unit generates
the parity bits to be stored into the local DRAM.
2.4 System BIOS ROM
If the system BIOS ROM is not shadowed, the ROM cycles are treated as
AT cycles. The system designer can put the ROM on the XD bus as an
8-bit slave or SD bus as a 16-Bit slave.
For a 16-bit slave, ROMCS# is connected to M16# through an open
collector driver such as a 7407, the 82C281/2 monitors M16# to
determine the width of the ROM data path.
2.5 I/O Ports located on the XD bus
For l/O ports located on the XD bus, the XDIR# is activated. I/O ports
0F0H - 0FFH are reserved for the coprocessor.
2.6 Refresh Cycles
The AT bus control unit arbitrates the hold request from 82C206 and
the refresh request from 82C281/2 internal, then decides which is the
next owner of the bus once the CPU relinquishes it. The refresh
request generated internally by 82C281/2 can be programmed as every
15.9 micro-seconds or every 95.5 micro-seconds for slow refresh
DRAM. lf the bus is granted for refresh cycles, the AT bus control
unit asserts RFSH# and MEMRD# commands and also generates the refresh
address.
2.7 DMA Cycles
The hold request from the 82C206 initiates DMA/Master transfers. The
82C281/2 performs the arbitration between HRQ and refresh
request. After the CPU acknowledges by asserting HLDA, and DMA request
wins the arbitration, the 82C281/2 sends HLDA1 to the 82C206
acknowledging the request. The 820206 then asserts DMA16# and
activates ADS16# to start 16-bit DMA transfers, or asserts DMA8# and
activates ADS8# to start 8-bit DMA transfers.
***Configurations:...
***Features:...
**82C283 386SX System Controller c:91...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94
***Notes:...
***Info:
OPTi's 82C822 VESA local bus to PCI Bridge (PCIB) chip is a high
integration 208-pin PQFP device designed to work with VESA VL bus
compatible core logic chipsets. The 82C822 PCIB provides interface to
the high performance PCI bus and is fully compliant to the PCI Version
2.0 specification. The 82C822 requires no glue logic to implement the
PCI bus interface and hence it allows designers to have a highly
integrated motherboard with both VESA local bus and PCI local bus
support. The PCIB chip offers premium performance and flexibility for
VESA VL-based desktop systems running up to 50MHz. The 82C822 PCIB can
be used with OPTi's 82C802G core logic and 82C602 buffer chipsets to
build a low cost and power efficient 486-based desktop solution. It
also works with OPTi 82C546/547 chipset to build a high performance
PCI/VL solution based on the Intel P54C processor.
The 82C822 PCIB provides all of the control, address and data paths to
access the PCI bus from the VESA Local bus (VL bus). The 82C822
provides a complete solution including data buffering, latching,
steering, arbitration, DMA and master functions between the 32-bit VL
bus and the 32-bit PCI bus.
The PCIB works seamlessly with the motherboard chipset bus arbiter to
handle all requests of the host CPU and PCI bus masters, DMA masters,
I/O relocation and refresh. Extensive register and timer support are
designed into the 82C822 to implement the PCI specification.
The 82C822 is a true VESA to PCI bridge. It has the highest priority
on CPU accesses after cache and system memory. It generates LDEV#
automatically and then compares the addresses with its internal
registers to determine whether the current cycle is a PCI cycle. When
a cycle is identified as PCI cycle, the 82C822 will take over the
cycle and then return RDY# to the CPU. If not, the 82C822 will give up
the cycle to the local device or, in the case of an ISA slave,
generate a BOFF# cycle to the CPU. This action will abort the cycle
and allow the CPU to rerun the cycle.
The 82C822 includes registers to determine shadow memory space, hole
locations and sizes to allow the 82C822 to determine which memory
space should be local and which is located on the ISA bus. Upon access
to memory, the 82C822 can determine whether or not the cycle is a PCI
access by comparing the cycle with its internal registers.
***Versions:...
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