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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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*OPTi...
**82C898         System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:
Overview
The 82C898 provides a highly integrated solution for fully compatible,
high performance PC/AT platforms. The 82C898 supports 486SX/DX/DX2/DX4
and  P24T  microprocessors  in  the  most  cost  effective  and  power
efficient designs  available today. For  high-end system applications,
this  device offers  optimum  performance for  systems  running up  to
50MHz.  

Based  fundamentally  on  OPTi’s   proven  82C801  and  82C802  design
architectures,  the 82C898 adds  additional memory  configurations and
extensive  power  management  control  for  the  processor  and  other
motherboard components.

The 82C898  supports the latest  in write-back processor  designs from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus  for compatibility  and performance.  It also  includes  an 82C206
Integrated Peripherals Controller (IPC),  all in a single 208-pin PQFP
(Plastic Quad Flat Pack) for low cost.

Power Management
Figure  2-1   [see  datasheet]  exemplifies  the   flexibility  of  an
82C898/82C602-based designs GREEN strategy.  System designs can easily
accommodate both  SLe and non-SLe  CPUs.  If  an Intel non-SLe  CPU is
used, SMI#, SMIAOT#, and FLUSH# are no connects. One design can easily
accommodate  both  types  of   processors  with  minimal  changes  for
upgrades.

***Configurations:...
***Features:...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
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*TI (Texas Instruments)...
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