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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91
***Info:
The HT21 is an advanced PC/AT compatible, single-chip 80386SX/80286
design solution. This highly integrated single chip allows simple,
low cost system design options while featuring high performance, low
power consumption, and minimum board space requirements. Advanced
memory management features include support for page mode, 2 or 4-way
interleaving in both pipelined and non-pipelined modes. The LIM 4.0
hardware implementation features dual sets of 32 registers with full
context support for highest performance Optimization of extended local
memory accesses. An advanced EMS hardware write-protect option is
provided. The HT21 supports 256K and 1M DRAMs in l by 1, 1 by 4, and 1
by 9 device configurations for up to 8MB of on-board system memory. A
flexible Shadow RAM option for System and Video BIOS as well as 8-
16-bit BIOS Options adds to overall design versatility.
A complete PC/AT compatible system with advanced features may be
implemented with minimal external support logic. The HT21 performs all
CPU and peripheral support functions in a single chip. Integrated
device functions include DMA Controllers, a Memory Mapper, Timers,
Counters, Interrupt Controllers, a Bus Controller and all supporting
circuitry for PC core logic requirements. The chip also contains all
the necessary address buffers, data transceivers, memory drivers,
parity checking and supporting circuitry for a complete high
performance computer solution. An asynchronous AT Bus clock allows for
a constant 8MHz Bus clock rate for highest bus device compatibility as
defined in IEEE Spec P996. In controlled bus applications the HT21
supports up to a 12 MHz Bus Clock rate. This device is packaged in a
208-pin Plastic Quad Flat Pack combining several external buffers into
this space saving solution.
***Configurations:...
***Features:...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92
***Notes:...
***Info:
The OPTi DXSLC was designed with two major objectives in mind. First,
support the high volume, high performance 386/486 VL market. Second,
be the most cost-efficient solution, even, in this extremely
competitive market. The DXSLC redefines chipset solutions for that
"value" market in a single broad-stroke.
The DXSLC vehicle provides all the above values - but still in, the
OPTi tradition of reliability, compatibility, support and service
throughout the design and after sales.
The DXSLC is designed to be the best combination of cost-effective
packaging and partitioning, while keeping the feature set robust.
The DXSLC is the "only" solution if you want to have a competitive
solution in today's and tomorrow's markets. [vomiting, too much
buzzword-laden marketing speech, Zero information]
The OPTi 495SLC is a "Super Low Cost", two chip solution offering
optimal performance for low to mid-range 386/486 based AT systems. The
OPTi 495SLC is designed for 386 systems running from 20, 25, 33 and 50
MHz. The 82C495SLC integrates a write-back cache controller, a local
DRAM controller, the CPU state machine, the AT bus state machine and
data buffers, all in a single 160-pin PFP. New on-chip hardware
provides the hooks for OPTi and VESA local bus device support.
***Configurations:...
***Features:...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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