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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT44          Secondary Cache                                c:Jun92
***Info:
The  HT44 is  a  look-aside write-through,  80486SX,  486DX or  486DX2
secondary cache  controller. It is  packaged in an  inexpensive 84-pin
plastic-leaded chip carrier (PLCC).

Architecture
With  its look-aside architecture,  the HT44  fits beside  the CPU-to-
Memory bus  and not in  the data path.   Therefore, once the  HT44 has
been designed  into a  486 system, it  can be populated  for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.

Performance
The  HT44  has a  number  of  performance  enhancing features.   These
include zero-waitstate burst line fills  to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.

Memory Configurations
The HT44 supports  cache sizes from 32KBytes to  1MB. Both synchronous
and asynchronous  SRAMs are supported.  25ns SRAMs are  sufficient for
zero-wait-state operation at 33MHz.

Chip Set Support
The HT44 can,  be implemented with minimal glue logic  in a 486 system
with the  HTK340 (code  name Shasta) chip  set.  The registers  in the
HTK340  allow  for programming  of  non-cacheable and  write-protected
areas of  memory. The  HTK340 will support  the HT44  with synchronous
SRAMs only.   Future Headland chip sets will  support both synchronous
and asynchronous SRAM designs.

The HT44  can also be used  with some third-party  chip sets, however,
additional glue logic may be required.

***Versions:...
***Features:...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:
The SL6012 Memory  Mapper is intended for use in  PC-AT design. It can
expand an address bus by 4  bits. In PC-AT applications, 4 bits of the
source  address   are  used  to  select   1  of  16,   eight  bit  map
registers. These registers  are normally programmed (through software)
with the  starting address of each  memory page. The  register data is
output directly for  use as the most significant  bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.

As shown  in Table 1  [see datasheet], the  SL6012 has three  modes of
operation; read, write and map. Data may be written into, or read from
the Memory  Mapper when  chip select CSN  is low. The  register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is  low, data is written  into a register from  the data bus. When
RWN is high  data is output from a Memory Mapper  register to the data
bus.

The map mode of operation is selected when chip select CSN is high. In
this mode, the  register data selected by the  map address inputs (MA0
through  MA3)  will be  available  on  the  map outputs  (MO0  through
MO7).  Note that  the map  registers are  addressed by  either  the RS
inputs or  the MA inputs depending  upon the operating  mode. When MEN
(Map Enable) is low the map  outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.

***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
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