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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91
***Info:
The HT22 is an advanced PC/AT compatible, single-chip 80386SX/80286
system design solution. This highly integrated single chip allows
simple, low cost system design options while featuring high perfor-
mance, low power consumption, and minimum board space require-
ments. Advanced memory management features include support for page
mode, 2 or 4-way interleaving in both pipelined and non-pipelined
modes. The EMS 4.0 hardware implementation features dual sets of 32
registers with full context support for highest performance
optimization of extended local memory accesses. An advanced EMS
hardware write-protect option has been added for maximum EMS 4.0
compatibility. The HTZ2 supports 256K, 1M and 4MB DRAMs in 1 by 1 and
1 by 4 device configurations for up to 20MB of on-board system memory.
16MB is addressed directly by system resources, the remainder
addressed by the EMS mode.
A flexible Shadow RAM option for System and Video BIOS as well as 8-
16-bit BIOS options adds to overall design versatility.
A complete PC/AT compatible system with advanced features may be
implemented with minimal external support logic. The HT22 performs all
CPU and peripheral support functions in a single chip. Integrated
device functions include DMA Controllers, a Memory Mapper, Timers,
Counters, Interrupt Controllers, a Bus Controller and all supporting
circuitry for PC core logic requirements. The chip also contains all
the necessary address buffers, data transceivers, memory drivers,
parity checking and supporting circuitry for a complete high
performance computer solution. An asynchronous AT Bus clock allows
for a constant 8MHz Bus clock rate for highest bus device compat-
ibility as defined in IEEE Spec P996. This device is packaged in a
208-pin Plastic Quad Flat Pack.
***Configurations:...
***Features:...
**HT25 3-volt Core Logic for 386SX c:Dec92
***Info:
The HT25 is the industry’s first 3-Volt single chip core logic with
integrated power management for 386SX based 3-Volt systems. Pro-
grammable power management features give system manufacturers the
flexibility of offering customized system solutions.
GENERAL DESCRIPTION
The HT25 is a PC/AT1M compatible single-chip solution with integrated
power management designed to operate in a 3-Volt system environment.
This highly integrated chip facilitates the design of low power, high
performance portable systems. The HT25 supports 3-Volt 386SX CPUs at
clock speeds up to 25MHz at 2.7V to 3.6V. It supports power
management functions using the System Management Mode (SMM).
Flexible power management is the cornerstone of the HT25. This
approach provides power saving features that can be customized for
product differentiation. Power management features include system
activity monitors and general purpose I/O pins. The HT25 generates
System Management Interrupt (SMI) to process activity information or
when access to powered down peripherals is detected. Further power
savings are achieved through the HT25’s ability to control CPU and NPU
clocks and support for slow refresh and self refresh DRAMs.
The HT25 Memory Controller features BIOS Shadowing, Memory Relocation,
EMS, Page Mode Memory Access and Interleaving. The memory controller
allows memory banks to be reordered to allow more efficient memory in-
terleaving. The HT25 supports 512Kb, le, and 4Mb DRAMs.
The HT25 architecture is optimized for 3-Volt system designs, the SD
bus acknowledge input provides a flexible I/O bus architecture and the
XD bus is buffered directly from the HT25. Further, no external data
bus buffers are required for a closed 3V system.
***Configurations:...
***Features:...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
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