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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
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**800 series...
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**GC101/102 12/16MHz PC/AT Compatible Chip Set c:Feb88
***Info:
The GC101/GC102 is a fully IBM PC/AT compatible chip set supporting
the 80286 CPU at clock Speeds up to 16MHz. This highly integrated
three chip solution features high performance, low power consumption,
low board space requirements, high reliability, and low cost. A fully
PC/AT compatible system maybe implemented with this chip set, the CPU,
Keyboard Controllers, RTC and 7 other devices plus memory. This chip
set supports 256K and 1 Mbit DRAMs in configurations up to 4 megabytes
at zero or one wait state. Zero wait state operations is supported up
to 12MHz and one wait at up to 16MHz.
The GC101 performs CPU and Peripheral support functions including that
of DMA Controllers, a Memory Mapper, Timers, Counters, Interrupt
Controllers, a Bus Controller, and their supporting circuitry. This
device is packaged in a 160 pin flat pack.
The GC102 maybe configured as either an Address Buffer or Data Buffer
by strapping one pin high or low. This chip replaces address buffers,
data transceivers, memory drivers, parity generators and supporting
circuitry. This device is packaged in an 84 pin PLCC
***Configurations:...
***Features:...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0 c:Jul89
***Notes:...
***Info:
The GC103 is a companion chip to the GC101/102 AT chip set. Replacing
the GC102 in its Address Buffer mode, this chip adds logic to fully
implement LIM, EMS 4.0. This device expands the capabilities of the
GC101/102 chip set. It adds support for up to 8MB of memory and
Shadow RAM for systems and video BIOS. The register-intensive design,
combined with the use of system memory, offers extremely high EMS
throughput compared with EMS systems using fewer mapping registers or
expansion memory. The GC103 contains a chip mapping register that
allows EMS to operate at full system speed without adding wait
states. With 2 sets of 32 EMS registers context switching in hardware
as well as software is supported.
The GC103 provides address buffering for the expansion bus, local I/O
bus, and the system board DRAM. Address , DMA, and Refresh controls
are included in the GC103. The chip integrates additional logic
previously implemented discretely in the GC101/102 board design. This
device is packaged in a 160 pin quad flatpack.
***Configurations:...
***Features:...
**GCK113 80386 AT Compatible Chip Set c:oct89...
**GCK181 Universal PS/2 Chip Set c:Mar89...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
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