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**M1217/M1209    386SX/SLC Single Chip (40MHz)    [no datasheet]   c91
***Notes:...
**M1219          386DX/486 ISA Cache? Single Chip [no datasheet]     ?
**M1419          386DX/486 ISA Cache  Single Chip [no datasheet]   c91
**Ml429/31/35    486 VLB/PCI/ISA      [no datasheet, some info] cOct93...
**M1439/31/45    486 VLB/PCI/ISA      [no datasheet, some info] <May95...
**M1489/87       FinALi-486 PCI Chipset                         <Feb95
***Info:
ALi's M1489/M1487 PCI chipset is  the most cost effective PCI solution
available. M1489/M1487  enables top-to-bottom PCI in  486 CPU systems,
offering superior price/performance for mainstream PCI-ISA systems.

M1489/M1487 highly  integrates the DRAM controller,  L2 cache control-
ler,  Host,  PCI, and  ISA  interface, as  well  as  the standard  ISA
functions:  DMA controller,  interrupt controller,  timer/counter, RTC
(Real Time Clock),  and keyboard controller. Additionally, M1489/M1487
incorporates the high performance Local  Bus IDE allowing a system de-
signer to implement Local bus IDE with no additional cost. M1489/M1487
is a  highly integrated  solution requiring minimized  TTL components,
enabling PCI-ISA designs at costs equal to or lower than comparable VL
Bus designs.

M1489 (Cache Memory PCI Controller:  CMP) integrates the L2 cache con-
troller  and  the  DRAM  controller.  The  cache  controller  supports
write-back cache  policies and cache size  from 128K to 1M  byte in an
interleaved  or non-interleaved  configuration.   The DRAM  controller
interfaces DRAM  to the Host  bus, PCI bus,  and Link bus.   M1489 can
support   EDO  3/5V   DRAM,   standard  DRAM,   and  flexible   timing
select. M1489  also integrates  intelligent Host to  PCI, PCI  to Host
buffer  to achieve high  performance.  Also,  M1489 provides  the high
performance Local Bus IDE interface.

M1487 (ISA Bridge Controller: IBC) provides the bridge between the ISA
bus, PCI  bus, and Host bus.  IBC integrates the  common I/O functions
found in  today's ISA  based systems: a  seven channel DMA,  two 82C59
interrupt controllers,  8254 timer/ counter, deep  green function, and
control logic for NMI generation. IBC also has built-in 128 bytes RTC,
MC14069, KBC,  and 7406.   IBC also provides  the decode  for external
BIOS.

***Configurations:...
***Features:...
**M????          Genie, Quad Pentium  [no datasheet, some info]    c95...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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