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**M1489/87 FinALi-486 PCI Chipset <Feb95
***Info:...
***Configurations:...
***Features:
Supported CPUs
o Supports AMD 486D4 and X5, Intel 486, P24T, P24D, DX4, SL-
Enhanced, Cyrix M7, UMC U5 and AMD AM486DXL CPUs in 25, 33, 40,
50, 66, 100 and 133 MHz 3V/5V CPU interface
o Supports CPU L1 writeback
o Supports Cyrix's linear addressing
L2 Cache Controller
o Write Back cache with standard SRAM
o 8 Tag Bit, always force Dirty or 7 Tag Bit, 1 Dirty bit
o Supports cache size of 128K to 1M with 32KX8, 64Kx8, 128Kx8
o Supports 2-1-1-1 read burst timing
o Write hit 0 wait support
DRAM Controller
o Supports 5V/3V EDO DRAM
o Flexible DRAM type & Timing support
o Supports up to 128M bytes, 4-bank DRAM size
o Supports hidden refresh and RAS only normal refresh
Built in RTC & KBC
o Built in 128 byte Real Time Clock (RTC) & MC14069
o Built in Keyboard Controller (KBC) & 7406
Built in IDE Controller
o Dedicated IDE pins, concurrent with PCI bus
o 4x32 bits Read-Ahead buffer and Write-Post buffer support
o Supports through ATA PIO mode 3, 4 harddisk
PCI Local Bus
o Synchronous 20, 25, 33 MHz PCI clock
o Supports PCI rev 2.0 with 4 PCI devices, 3 slot PCI masters, 1
slot PCI slave
o Supports 4 PCI interrupt steering input
o Supports CPU to PCI 4 layer DWord write buffer
o Supports PCI to memory 8 layer DWord write buffer
o Supports PCI parity
Power Management
o Deep Green SMM, SMI
o Suspend switch support, Green mode state is LED indicated
o CLKCTR for clock generator control
Process/Packing
o M1489 0.6u, 208-pin PQFP
o M1487 0.6u, 160-pin PQFP
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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