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**93C488         5x86/486 Single Chip PCI controller            <Aug96
***Info:...
***Configurations:...
***Features:
o   Support processor bus up to 50MHz.
    - AMD 5x86-133, 486DX4-120/100, 486DX2-80/66, 486DX-50/40/33/25
    - Cyrix/IBM/ST 5x86-120/100, 486DX4-120/100, 486DX2-80/66/50, 
      486DX-40/33/25
    - TI 486DX4-100, 486DX2-80/66
    - Intel 486DX4-100/75, 486DX2-66, 486DX-40/33/25, 486SX
o   Integrated DRAM controller
    - 1Mbyte to 256Mbyte main memory
    - Non-page mode, Fast page mode, Nibble mode, Write per bit mode, 
      EDO mode DRAM providing flexible timing control
    - Supports for auto detection of memory type including size, 
      refresh cycle.
    - 4 RAS lines for 4 DRAM banks
    - Supports for symmetrical and asymmetrical DRAM addressing
    - Supports RAS only, CBR hidden refresh
    - Supports shadow memory and 384K relocated memory
o   Integrated synchronous cache controller
    - 128Kbyte to 1Mbyte cache
    - Support pipeline/non-pipeline burst SSRAM
    - Support X,1,1,1/X,2,2,2 burst cycle
o   Fast IDE interface
    - Supports up to PIO mode 4 Timings
    - Separate master/slave IDE mode support
    - Supports primary/secondary port address swapping
o   PCI bus controller
    - 4 level host to PCI write buffer
    - Supports host to PCI byte merging
    - Supports two PCI bus master
o   Integrated IPC includes
    - Two 8259 interrupt controllers
    - Two 8237 DMA controllers
    - One 8254 timer/counter
    - RTC
    - Keyboard controller
o   Power management
    - Programmable hardware events
    - Programmable CPU clock control (STPCLK#)
    - Slow down system clock speed (SLOWDWN#)
o   Single chip 208 pin QFP

*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in the configurations section  and below have been sourced
from the second.

"Although the 82497 Cache Controller  is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache  Controller is part  of the  Pentium Processor  (510\60, 567\66)
Chip  Set, the  two parts  are functionally  identical except  for the
differences noted in this section." - p491

Aside  from some  minor  differences in  pin  configuration, the  main
difference is the direct support  for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.


This  chip was  used on  the Pentium  90MHz CPU  complexes of  Intel's
Xpress  platform.   Specifically  the BXCPUPENT90  (Single  90MHz,  16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.

***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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