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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90
***Notes:...
***Info:
The 82485 is  a second-level cache controller designed  to improve the
performance  of  Intel486  Microprocessor  systems.  One  82485  cache
controller supports  64K or  128K bytes of  second level  cache memory
that maps  to the  entire 4 Gigabytes  of the  Intel486 microprocessor
address space. The controller  is completely software transparent. One
controller plus SRAMs  provides a 64K or a  128K cache. External EPROM
can  be  cached  yet  remain  write protected.   The  82485  is  fully
compatible  with the  Intel486  microprocessor. All  Intel486 CPU  bus
cycles and timings are supported.

A complete, optional second level  cache controller using the 82485 is
available  as the 485Turbocache  Module from  Intel (data  sheet order
number 240722).

2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically  to interface with  the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or  a non-sectored configuration  (one line per tag).   The 82485
will directly support a nonsectored  64K data cache or a 128K sectored
data cache.  Both the 64K and  128K configurations are able to map the
entire 4 gigabytes of  the Intel486 microprocessor address space.  The
82485 interfaces directly to  the Intel486 microprocessor.  All Intel-
486 CPU bus cycles and timings are supported.  The 82485 also supports
0 wait  state processor operation  when there is  a cache hit  and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations.  The controller  is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the  system bus), so it supports  the same cache consistency
mechanisms as the  Intel486 CPU.  The controller also  provides a safe
method to cache ROM BIOS through the  use of a write protect pin and a
write protect strapping option.

The data cache  (Static RAM) resides external to  the 82485. The 82485
provides all  controls for  the SRAMs.  No  external latches  or tran-
ceivers are  required.  The 82485  output buffers support up  to eight
SRAMs.  A  64K cache can be  designed with only  five components; nine
components for a 128K cache.  Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.

The  82485  can  be  used  to  design  a  custom  second  level  cache
configuration. For an easier system design and higher integration, the
82485M Turbocache  can be used  (see data sheet order  number 240722).
This  module is  a  complete second  level  cache in  one package.  It
consists  of a single  82485 cache  controller and  SRAM to  provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.

***Versions:...
***Features:...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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