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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o 50 MHz Intel486 DX CPU
- RISC Integer Core with Frequent Instructions Executing in One
Clock
- 160 Mbyte/Sec Burst Bus
- 41 Dhrystone MIPs
- 11.5M Double Precision Whetstones/Sec.
- On-Chip Cache and FPU
o Highly Flexible
- Supports 128 Kbyte and 256 Kbyte Configurations
- Complete MESI Protocol Support
- 32- or 64-Bit Memory Bus Width
- Synchronous, Asynchronous, and Strobed Memory Bus Protocols
- Variable Cache Line Sizes and Sectoring
- Cache Data Parity Option
o High Performance Second Level Cache
- Two-Way Set Associative
- Write-Back or Write Through Cache
- Zero Wait State Cache Access
- Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o Full Multiprocessing Support
- Implements MESI Write-Back Cache Protocol
- Low Bus Utilization
- Automatically Maintains 1st Level Cache Consistency
- Supports Read-for-Ownership, Write-Allocation, and Cache-to-
Cache Transfers
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*Unresearched:...
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*VLSI...
**VL82C594/596/597 Wildcat c95
***Notes:...
***Info:
Wildcat is a 586-class PCI chipset comprised of the VL82C594 System
Controller, two VL82C595 Data Buffers, and the VL82C596/VL82C597 ISA
Bridge. The VL82C596 is for single processor systems using a P5, P54C,
P54CS, P55C, K5, or M1 CPU. The VL82C597 includes the Intel IO APIC
for use in Intel-based dual processor systems. The VL82C594 supports
up to 1G of fast page mode or EDO DRAM. It also supports up to 1M of
async, sync, or PBSRAM. The VL82C595 data buffers work with the
VL82C594 to provide 3smart2 write buffering to yield exceptional
performance with or without an L2 cache. The VL82C596/597 acts as a
PCI-ISA bridge and incorporates advanced power management features and
a Real-Time Clock with integrated write protection.
***Configurations:...
***Features:...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
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**Other:...
**Not sure if they actually exist...
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