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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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**W83769          Local Bus IDE Solution                           <94
***Info:
GENERAL DESCRIPTION

The W83769  is a  high-performance, low-cost, highly  integrated logic
design  for IDE hard  disk applications  in PCI  (Peripheral Component
Interconnect)  local  bus systems.  It  provides  a  bridge between  a
standard  IDE  drive  and the  PCI  local  bus.  The W83769  is  fully
compatible  with the  ANSI ATA  3.0 specifications  for IDE  hard disk
operation  and the  PCI SIG  revision 2.0  specifications for  the PCI
local bus  protocol. Packaged in  a 100-pin PQFP, the  W83769 directly
supports the 32-bit PCI bus without requiring any external TTLs.

The W83769  operates at up to 50  MHz and provides a  full 32-bit data
path to the PCI bus. Doubleword read and write operations are provided
via  internal   control  and  conversion  logic.   Write  posting  and
read-ahead  allows CPU  memory  cycles to  run  concurrently with  IDE
cycles and improves the hard disk buffer-to-host transfer rate.

The IDE  drive interface timing  of the W83769 is  completely software
programmable,  including command  active/recovery  timing and  address
setup-hold   timing  for   each  drive.   The  device   supports  Fast
ATA/Enhanced  IDE  mode  3  timing  and IORDY  monitoring  for  better
performance.   The  W83769  directly  supports four  IDE  drives  with
170/1F0   dual   IDE  connectors.   The  IO base   addresses  of   the
primary/secondary  IDE connector  are exchangeable  by  power-on strap
option.

***Versions:...
***Features:...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
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