[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90
***Info:
Introduction.
The CS8233 PEAK/386 AT CHIPSet is a three chip VLSI implementation of
most of the system logic required to implement a CACHE BASED iAPX
386DX based system. The CHIPSet is designed to offer a 100% PC AT
compatible integrated solution. The flexible architecture of the
CHIPSet allows it to be used in any iAPX386DX based system design,
such as CAD/CAE workstations, office systems, industrial and financial
transaction systems. The CS8233 PEAK/386 AT CHIPSet provides a
complete CACHE BASED 386/AT system using only 19 components plus
memory device. The CS8233 PEAK/386 AT CHIPSet consists of one 82C31l
CPU/Cache/DRAM Controller, one 82C315 Bus Controller, and one 82C316
Peripherals Controller. The CHIPSet supports a local CPU bus, a 32-bit
system memory bus, and AT buses as shown in the system diagram [see
data sheet]. The 82C311, 82C315, and 82C316 are all available in 160
pin PFP package.
The 82C311 CPU/Cache/DRAM Controller
The 82C311 provides the generation and synchronization of control
signals for all buses. The 82C311 also supports an independent AT bus
clock, and allows selection of different processor and AT bus clock
speed.
The 82C311 contains a high performance and high integration Cache/DRAM
controller designed to interface directly to the 80386DX micro-
processor. By integrating Cache/DRAM control functions on-chip,
simultaneous activation of cache and DRAM accesses minimize the cache
miss cycle penalty.
The 82C311 Cache Controller supports a two-way set associative cache
architecture and cache sizes of either 32KB, 64KB or 128KB. It
implements a buffered-write through scheme and a Least Recently Used
(LRU) replacement algorithm.
The 82C311 also has hardware support to allow the user to designate up
to four blocks (of variable size from 4KB to 4MB) of main memory as
non-cacheable address space. This feature is important for
compatibility issues when operating in a multi-processing LAN
environment, dual-port memory environment, and non-caching of video
RAM. In addition, this feature eliminates the need to use very fast
PALS externally to decode non-cacheable regions and gives the user
much more flexibility.
82C315 Bus Controller
The 82C315 Bus Controller contains the data buffers used to interface
between the local, system memory and AT data buses. In addition to
having high current drive, they also perform the conversion necessary
between the different sized data paths. The 82C315 also includes all
the interface logic required to directly interface to the 80387DX and
Weitek 3167 co-processors with no additional discrete logic required.
82C316 Peripheral Controller
The 82C316 Peripheral Controller contains the address buffers used to
interface between all address buses and the addresses needed for
proper data path conversion. In addition to integrating a variety of
TTL/SSI interface logic, the 82C316 includes the equivalent of the
82C206 Integrated Peripheral Controller (IPC). The IPC section
contains:
o Two (2) 82387 DMA controllers [sic, should be 8237A?]
o Two (2) 8259 interrupt controllers
o One (1) 8254 timer/counter
o One (1) MC146818 real time clock
o One (1) memory mapper
***Configurations:...
***Features:...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved