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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97
***Info:
Nowadays, several PC form factors exist in the PC board market, such
as NLX, LPX, ATX and Baby-AT form factors. Due to the different
placements of the form factor, PC chipsets should be prepared for
different board layouts. As a result, SiS chips based on compatible
logic design provide two series of chipsets, SiS 5597 and SiS 5598, to
assist board designers for their board layouts.
SiS 5597’s pin assignment is based on NLX, and LPX form factor, while
SiS 5598’s is defined on the basis of ATX and Baby-AT form factors. In
the next few chapters, you will read “SiS Chip” which indicates either
SiS 5597 or 5598 chipsets, decided by the placements of form factors
on PC boards of customers.
The SiS Chip with built-in VGA controller is a highly integrated
single chip solution for Pentium PCI/ISA system. A portion of on-board
DRAM is shared with the integrated VGA controller. In that way, the
system cost is substantially reduced and on-board DRAM can be used
flexibly.
The SiS Chip consists of Host-to-PCI bridge function, PCI to ISA
bridge function, PCI IDE function, Universal Serial Bus host/hub
function, Integrated RTC, Integrated Keyboard Controller and Graphics/
Video accelerate function.
SiS Chip supports Enhanced Power Management, including legacy Power
Management Unit and Advanced Configuration and Power Interface
(ACPI). It also supports ATA Synchronous DMA transfer protocol to
improve the IDE performance and Common Architecture for moving ISA
function to PCI to improve system performance.
***Configurations:...
***Features:...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
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*UMC...
*Unresearched:...
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*Winbond...
*ZyMOS...
*General Sources:...
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