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**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87
***Notes:...
***Info:
The 82380 is a multi-function support peripheral that integrates
system functions necessary in an 80386 environment. It has eight
channels of high performance 32-bit DMA with the most efficient
transfer rates possible on the 80386 bus. System support peripherals
integrated into the 82380 provide Interrupt Control, Timers, Wait
State generation, DRAM Refresh Control, and System Reset logic.
The 82380's DMA Controller can transfer data between devices of
different data path widths using a single channel. Each DMA channel
operates independently in any of several modes. Each channel has a
temp orary data storage register for handling non-aligned data without
the need for external alignment logic.
The 82380 contains several independent functional modules. The foll-
owing is a brief discussion of the components and features of the
82380. E$ch module has a corresponding detailed section later in this
data sheet. Those sections should be referred to for design and
programming information.
82380 Architecture:
The 82380 is comprised of several computer system functions that are
normally found in separate LSI and VLSI components. These include: a
high-performance, eight-channel, 32-bit Direct Memory Access Cont-
roller; a 20-level Programmable Interrupt Controller which is a super-
set of the 82C59A; four 16-bit Programmable Interval Timers which are
functionally equivalent to the 82C54 timers; a DRAM Refresh Cont-
roller; a Programmable Wait State Generator; and system reset
logic. The interface to the 82380 is optimized for high-performance
operation with the 80386 microprocessor.
The 82380 operates directly on the 80386 bus. In the Slave mode, it
monitors the state of the processor at all times and acts or idles
according to the commands of the host. It monitors the address
pipeline status·. and generates the programmed number of wait states
for the device being accessed. The 82380 also has logic to reset the
80386 via hardware or software reset requests and processor shutdown
status.
After a system reset, the 82380 is in the Slave mode. It appears to
the system as an I/O device. It becomes a bus master when it is
performing DMA transfers.
To maintain compatibility with existing software, the registers within
the 82380 are accessed as bytes. If the internal logic of the 82380
requires a delay before another access by the processor, wait states
are automatically inserted into the access cycle. This allows the
programmer to write initialization routines, etc. without regard to
hardware recovery times.
***Versions:...
***Features:...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97
***Notes:...
***Info:
The Intel 380FB PCIset (380FB) consists of the 82380FB Mobile
PCI-to-PCI Bridge (MPCI2) and the 82380AB Mobile PCI-to-ISA Bridge
(MISA). The 380FB supports four PCI slots and three ISA slots. The
MPCI2 and MISA can also be used individually to provide either PCI
slot expansion or ISA slot expansion.
The 380FB supports a full Hot Docking capable docking station with 5V
PCI and ISA add-in expansion slots. MPCI2 provides the docking con-
trol for hot insertion, power management, and a PCI-to-PCI bridge to a
5V PCI desktop style add-in bus. Internal arbitration supports four
bus masters on the secondary PCI bus. The PC/PCI arbitration interface
logic provides PC/PCI bridge support. The 380FB controls all docking,
undocking and suspend/resume sequences for the docking station. The
EPROM interface logic provides an industry standard interface to a
non-volatile memory device (EPROM) for supporting dynamic
autoconfiguration of a previously configured notebook/docking station
combination. The Power management logic provides a control and status
interface between the docking station and notebook that allows the
docking station to control the state of the notebook. A non-volatile
memory interface is used to store docking identification and notebook
configuration information to speed dynamic configuration for a
pre-configured notebook docking combination.
MPCI2 supports the PCI bus enumeration mechanism for PCI-to-PCI
bridges. This is needed to support the Windows 95 dynamic
configuration of system resources when the system docks or
undocks. Otherwise, the operating system must reset the system after
reconfiguration. The undocking mechanism of the 380FB guarantees a
safe notebook removal. Event notification allows docking resources to
be dynamically removed and applications gracefully shut down, if
needed. A hardware mechanism is provided to indicate when the notebook
is prepared to undock. This can be used to eject or unlock the
notebook from the docking station.
The MPCI2’s subtractive decoding guarantees that all accesses targeted
for a downstream ISA bridge (such as the MISA) arrive at their
destination. Software does not need to determine the devices on the
ISA bridge and then program positive decode ranges (as is needed on
traditional positive decode bridges).
***Versions:...
***Features:...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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