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**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93
***Notes:
Information taken from:  82420_PCIset_ISA_and_EISA_Bridges_Mar93.pdf
                                Intel_Peripheral_Components_1994.pdf*
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*2
                                                  82378 (Mar-96).pdf
   (Errata:1) http://support.intel.com/support/chipsets/420/8510.htm*3
   (Errata:2) http://support.intel.com/support/chipsets/420/8511.htm*3

>*  datasheet for 82378 is dated Oct'93
>*2 datasheet for 82378 is dated Dec'94
>*3 see archived sources at the end of this section

The March '93  source makes no mention of  the ZB variant, indicating
it  was released  after this  date. The  Oct'93 datasheet  is  only 2
pages,  a full  length version  could not  be found.  Most differences
between  the Mar'93  and  the Oct'93  are  indicated in  the text.  In
addition, the  Mar'93 refers to  the 82378IB specifically,  the Oct'93
refers to the  82378 in general, and briefly  explains the differences
between the IB and ZB variants.

The main  difference between the IB  and ZB variants is  the number of
supported PCI masters and interrupts. The mar'93 datasheet claims that
the  IB variant  supports four.   The  Oct'93 source  updates this  by
claiming it  only supports  two and  states that  only the  ZB variant
supports four.   Perhaps the  Mar'93 datasheet is  a misprint,  or the
chip didn't meet it's intended specification.

In  Errata:1, more  specifics are  given. Dated  Aug'93 the  following
diff- erences are given:
"
82378IB   * Name change from 82378IB to 82378ZB
Changes:  * ZB eliminates all known IB errata
	  * Features/Enhancements include: Interrupt Steering Logic, 
            System Management Mode (SMM), leadframe change from copper 
            to Alloy 42.
Timing:
We  anticipate  production  shipments  for  the 82378ZB  to  begin  in
December 1993..."

Errata:2 gives further  details.  The document itself  is undated, but
Errata:1 is  hyperlinked to it.   Its text  is quoted in  the Versions
section.

The  Dec'94 datasheet  makes no  mention  of either  variant, it  just
refers to the 82378. It would  appear that this is the ZB variant. The
biggest change  is again  to the  PCI masters. Now  it supports  6 PCI
masters  and still  4 PCI  interrupts. It  also now  supports Advanced
Power Management. Differences  are shown in the text.   There are some
additional insignificant minor differences in the text not shown.

The Mar'96  datasheet again refers  to the 82378ZB  specifically. This
indicates that  the chip  described in the  Dec'94 is *likely*  the ZB
variant. This datasheet describes the 82378ZB and the 82379AB. Changes
in this datasheet have not been added to the quoted text below.


Archived sources:
http://web.archive.org/web/20000816013859/http://support.intel.com/support/chipsets/420/8510.htm
http://web.archive.org/web/20000816013854/http://support.intel.com/support/chipsets/420/8511.htm

***Info:...
***Versions:...
***Features:...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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