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*ACC Micro...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications c96
***Info:...
***Configurations:...
***Features:
o Supports Intel P54C, Cyrix M1, and AMD K5
- Linear burst support
- 64-bit Pentium class CPU with 66 MHz bus frequency
o ACC Micro Power Management Control
- SMM/SMI support
- Individual sets of system events and break events such as for
Global Standby, Local Standby, Suspend, and Doze control.
- Dedicated external SMI trigger inputs such as for battery
monitoring, suspend/resume button, and AC power.
- Software SMI
- Warning Timer for SMI
- Patented 'Adaptive Thermal Control' with auto-control or SMI
generation
- Shadow Registers for suspend to disk
- Suspend to DRAM
- CPU/PCI/ISA individually suspend/powered-down
- Stop clock protocol, STPCLK#
- 0 Hz suspend
- PCI suspend for Warm Docking
o Mobile PC, or PC/PCI
- CLKRUN# protocol to reduce PCI power consumption
- Serialized interrupt protocol, SIN#/SOUT# for interrupt routing
in docking design
- Serialized DMA protocol for DRQ routing in docking design
o Synchronous/asynchronous PCI bus
- Synchronous PCI clock at CPUCLK/2
- Asynchronous PCI clock
- Four PCI bus masters
- Converts back to back sequential CPU to PCI memory writes to PCI
burst writes
- Bytes merge for CPU to PCI memory write
- Eight Dwords deep of CPU to PCI posted write buffers
- Four Dwords pre-fetch buffers for CPU read from PCI memory
- PCI to DRAM posting 8 Qwords deep
- PCI from DRAM pre-fetched buffers 4 Qwords deep
- Pre-snoop capability for PCI to DRAM with bandwidth of 119 MB/s
- 3V or 5V PCI bus
o Built-in DRAM controller
- Five banks of DRAM, up to 512MB main memory
- Self-Refresh DRAM support
- EDO or Fast Page Mode DRAM
- Five RAS and 12 MA lines
- Symmetrical/Asymmetrical DRAMs
- 64-bit data path to memory
- 64-bit DRAM option for individual bank
- Four Qword posted write buffers for x-1-1-1 DRAM write cycles
- Support 3V or 5V DRAM
o Built-in level 2 cache controller
- Direct mapped write back/write through
- Up to 2MB
- Burst, pipelined burst, or standard SRAM
- Cache hit read/write x-1-1-1-1-1 ... with pipelined burst SRAM
o Built-in full-blown ISA bus interface
- Integrated 8254x1, 8259x2, 8237x2
- Programmable ISA bus speed
- Independent edge/level triggered interrupt controller
- Optional Type-F DMA
- X-bus support for chip select decode
- Flash EPROM support
- Dedicated ISA cycles option to free up the PCI bus
o Integrated Fast IDE interface
- Enhanced PCI IDE
- Support master/DMA mode IDE
- Built-in 8 Dwords posted write buffer
- Built-in 8 Dwords pre-fetched buffer
- Four independently programmable register sets for IDE timing
control
o Built-in 64-bit data path
**ACC2056 ?Pentium 3.3V Notebook [no datasheet]<Jan96...
**ACC2057 PCI Notebook/Embedded Single Chip [no datasheet]<Aug96...
**ACC2066NT 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2086 486 VL-based System Super Chip Soluti[no datasheet] ?...
**ACC2087 Enhanced Super Chip (486 Single Chip) <Aug96...
**ACC2089 486 PCI-based System Super Chip [no datasheet] ?...
**ACC2168/GT 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2178A 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2268 ?486 [no datasheet] ?...
**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
**
**Support Chips:
**ACC2016 Buffer and MUX Logic c96
***Info:
The ACC Micro 2016 is designed to work together with the system core
logic products to provide the decoding logic for the Real Time Clock
(RTC), address buffer, and data buffer for the 486/386DX and Pentium
applications. At least seven TTLs can be saved when using the 2016.
The 2016 can be used with either the 2268/2178/2168/2056/2057/
2066/2048 system logic or the 2086/2087/2089 super chip. The 2016 is
based on the condition of the /ROMCS signal to determine which system
logic to work with. During power up, if the /ROMCS is pulled high, it
works with the 2268/2178/2168/2056/2057/2066/2048 system logic. If
/ROMCS is pulled low, it works with the 2086/2087/2089 super chip. The
/RTCDS signal (pin 97) requires a pull low through a damping register
for all system logic applications.
***Versions:...
***Features:...
**ACC2020 Power Management Chip c92...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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