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**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97
***Notes:...
***Info:...
***Versions:...
***Features:
o Supported Kits for both Pentium and Pentium II Microprocessors
- 82430TX ISA Kit
- 82440LX ISA/DP Kit
o Multifunction PCI to ISA Bridge
- Supports PCI at 30 MHz and 33 MHz
- Supports PCI Rev 2.1 Specification
- Supports Full ISA or Extended I/O (EIO) Bus
- Supports Full Positive Decode or Subtractive Decode of PCI
- Supports ISA and EIO at 1/4 of PCI Frequency
o Supports both Mobile and Desktop Deep Green Environments
- 3.3V Operation with 5V Tolerant Buffers
- Ultra-low Power for Mobile Environments Support
- Power-On Suspend, Suspend to RAM, Suspend to Disk, and Soft-
OFF System States
- All Registers Readable and Restorable for Proper Resume
from 0.V Suspend
o Power Management Logic
- Global and Local Device Management
- Suspend and Resume Logic
- Supports Thermal Alarm
- Support for External Microcontroller
- Full Support for Advanced Configuration and Power Interface
(ACPI) Revision 1.0 Specification and OS Directed Power
Management
o Integrated IDE Controller
- Independent Timing of up to 4 Drives
- PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec
- Supports "Ultra DMA/33" Synchronous DMA Mode Transfers up to
33 Mbytes/sec
- Integrated 16 x 32-bit Buffer for IDE POI Burst Transfers
- Supports Glue-less "Swap-Bay" Option with Full Electrical
Isolation
o Enhanced DMA Controller
- Two 82C37 DMA Controllers
- Supports PCI DMA with 3 PC/PCI Channels and Distributed DMA
Protocols (Simultaneously)
- Fast Type-F DMA for Reduced PCI Bus Usage
o Interrupt Controller Based on Two 82C59
- 15 Interrupt Support
- Independently; Programmable for Edge/Level Sensitivity
- Supports Optional I/O APIC
- Serial Interrupt Input
o Timers Based on 82C54
- System Timer, Refresh Request, Speaker Tone Output
o USB
- Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec
- Supports Legacy Keyboard and Mouse Software with USB-based
Keyboard and Mouse
- Supports UHCI Design Guide
o SMBus
- Host Interface Allows CPU to Communicate Via SMBus
- Slave Interface Allows External SMBus Master to Control
Resume Events
o Real-Time Clock
- 256-byte Battery-Back CMOS SRAM
- Includes Date Alarm
- Two 8-byte Lockout Ranges
o Microsoft Win95 Compliant
o 324 mBGA Package
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C822 PCIB (VLB-to-PCI bridge) c:94
***Notes:...
***Info:
OPTi's 82C822 VESA local bus to PCI Bridge (PCIB) chip is a high
integration 208-pin PQFP device designed to work with VESA VL bus
compatible core logic chipsets. The 82C822 PCIB provides interface to
the high performance PCI bus and is fully compliant to the PCI Version
2.0 specification. The 82C822 requires no glue logic to implement the
PCI bus interface and hence it allows designers to have a highly
integrated motherboard with both VESA local bus and PCI local bus
support. The PCIB chip offers premium performance and flexibility for
VESA VL-based desktop systems running up to 50MHz. The 82C822 PCIB can
be used with OPTi's 82C802G core logic and 82C602 buffer chipsets to
build a low cost and power efficient 486-based desktop solution. It
also works with OPTi 82C546/547 chipset to build a high performance
PCI/VL solution based on the Intel P54C processor.
The 82C822 PCIB provides all of the control, address and data paths to
access the PCI bus from the VESA Local bus (VL bus). The 82C822
provides a complete solution including data buffering, latching,
steering, arbitration, DMA and master functions between the 32-bit VL
bus and the 32-bit PCI bus.
The PCIB works seamlessly with the motherboard chipset bus arbiter to
handle all requests of the host CPU and PCI bus masters, DMA masters,
I/O relocation and refresh. Extensive register and timer support are
designed into the 82C822 to implement the PCI specification.
The 82C822 is a true VESA to PCI bridge. It has the highest priority
on CPU accesses after cache and system memory. It generates LDEV#
automatically and then compares the addresses with its internal
registers to determine whether the current cycle is a PCI cycle. When
a cycle is identified as PCI cycle, the 82C822 will take over the
cycle and then return RDY# to the CPU. If not, the 82C822 will give up
the cycle to the local device or, in the case of an ISA slave,
generate a BOFF# cycle to the CPU. This action will abort the cycle
and allow the CPU to rerun the cycle.
The 82C822 includes registers to determine shadow memory space, hole
locations and sizes to allow the 82C822 to determine which memory
space should be local and which is located on the ISA bus. Upon access
to memory, the 82C822 can determine whether or not the cycle is a PCI
access by comparing the cycle with its internal registers.
***Versions:...
***Features:...
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