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**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97
***Notes:...
***Info:
The 82371AB PCI ISA IDE Xceierator (PIIX4) is a multi-function PCI
device implementing a PCI-to-ISA bridge function, a PCI IDE function,
a Universal serial Bus host/hub function, and an Enhanced Power
Management function. As a PCI-to-ISA bridge, PIIX4 integrates many
common, I/O functions found in ISA-based PC systems-two 82C37 DMA
Controllers, two 82C59 interrupt Controllers, an 82C54 Timer/Counter,
and a Real Time Clock. In addition to compatible transfers, each DMA
channel supports Type F transfers. PIIX4 also contains full support
tor both PC/PCI and Distributed DMA protocols implementing PCI-based
DMA. The interrupt Controller has Edge or Level sensitive programmable
inputs and fully supports the use of an external I/O Advanced
Programmable interrupt Controller (APIC) and Serial interrupts. Chip
select decoding is provided for BIOS, Real Time Clock, Keyboard
Controller, second external microcontroller, as well as two
Programmable Chip Selects. PIIX4 provides full Plug and Play
compatibility. PIIX4 can be configured as a Subtractive Decode bridge
or as a Positive Decode bridge. This allows the use of a subtractive
decode PCI-to-PCI bridge such as the Intel 380FB PCIset which
implements, a PCI/ISA docking station environment.
PIIX4 supports two IDE connectors for up to four IDE devices providing
an interface for IDE hard disks and CD ROMS. Up to four IDE devices
can be supported in Bus Master mode. PIIX4 contains support for
"Ultra DMA/33" synchronous DMA compatible devices.
PIIX4 contains a Universal Serial Bus, (USB) Host Controller that is
Universal Host Controller interface (UHCI) compatible. The Host
Controller's root hub has two programmable USB ports.
PIIX4 supports Enhanced Power Management, including full Clock
Control, Device Management for up to 14 devices, and Suspend and
Resume logic with Power On Suspend, Suspend to RAM or Suspend to Disk,
It fully supports Operating System Directed Power Management via the
Advanced Configuration and Power Interface (ACPI) specification.
PIIX4 integrates both a System Management Bus (SMBus) Host and Slave
interface for serial communication with other devices.
***Versions:...
***Features:...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*OPTi...
**82C822 PCIB (VLB-to-PCI bridge) c:94
***Notes:...
***Info:
OPTi's 82C822 VESA local bus to PCI Bridge (PCIB) chip is a high
integration 208-pin PQFP device designed to work with VESA VL bus
compatible core logic chipsets. The 82C822 PCIB provides interface to
the high performance PCI bus and is fully compliant to the PCI Version
2.0 specification. The 82C822 requires no glue logic to implement the
PCI bus interface and hence it allows designers to have a highly
integrated motherboard with both VESA local bus and PCI local bus
support. The PCIB chip offers premium performance and flexibility for
VESA VL-based desktop systems running up to 50MHz. The 82C822 PCIB can
be used with OPTi's 82C802G core logic and 82C602 buffer chipsets to
build a low cost and power efficient 486-based desktop solution. It
also works with OPTi 82C546/547 chipset to build a high performance
PCI/VL solution based on the Intel P54C processor.
The 82C822 PCIB provides all of the control, address and data paths to
access the PCI bus from the VESA Local bus (VL bus). The 82C822
provides a complete solution including data buffering, latching,
steering, arbitration, DMA and master functions between the 32-bit VL
bus and the 32-bit PCI bus.
The PCIB works seamlessly with the motherboard chipset bus arbiter to
handle all requests of the host CPU and PCI bus masters, DMA masters,
I/O relocation and refresh. Extensive register and timer support are
designed into the 82C822 to implement the PCI specification.
The 82C822 is a true VESA to PCI bridge. It has the highest priority
on CPU accesses after cache and system memory. It generates LDEV#
automatically and then compares the addresses with its internal
registers to determine whether the current cycle is a PCI cycle. When
a cycle is identified as PCI cycle, the 82C822 will take over the
cycle and then return RDY# to the CPU. If not, the 82C822 will give up
the cycle to the local device or, in the case of an ISA slave,
generate a BOFF# cycle to the CPU. This action will abort the cycle
and allow the CPU to rerun the cycle.
The 82C822 includes registers to determine shadow memory space, hole
locations and sizes to allow the 82C822 to determine which memory
space should be local and which is located on the ISA bus. Upon access
to memory, the 82C822 can determine whether or not the cycle is a PCI
access by comparing the cycle with its internal registers.
***Versions:...
***Features:...
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